src/soc/logical/test/test_pipe_caller.py

   1 from nmigen import Module, Signal
   2 from nmigen.back.pysim import Simulator, Delay, Settle
   3 from nmigen.test.utils import FHDLTestCase
   4 from nmigen.cli import rtlil
   5 import unittest
   6 from soc.decoder.isa.caller import ISACaller, special_sprs
   7 from soc.decoder.power_decoder import (create_pdecode)
   8 from soc.decoder.power_decoder2 import (PowerDecode2)
   9 from soc.decoder.power_enums import (XER_bits, Function)
  10 from soc.decoder.selectable_int import SelectableInt
  11 from soc.simulator.program import Program
  12 from soc.decoder.isa.all import ISA
  13
  14
  15 from soc.logical.pipeline import LogicalBasePipe
  16 from soc.alu.alu_input_record import CompALUOpSubset
  17 from soc.alu.pipe_data import ALUPipeSpec
  18 import random
  19
  20
  21 class TestCase:
  22     def __init__(self, program, regs, sprs, name):
  23         self.program = program
  24         self.regs = regs
  25         self.sprs = sprs
  26         self.name = name
  27
  28 def get_rec_width(rec):
  29     recwidth = 0
  30     # Setup random inputs for dut.op
  31     for p in rec.ports():
  32         width = p.width
  33         recwidth += width
  34     return recwidth
  35
  36 def set_alu_inputs(alu, dec2, sim):
  37     # TODO: see https://bugs.libre-soc.org/show_bug.cgi?id=305#c43
  38     # detect the immediate here (with m.If(self.i.ctx.op.imm_data.imm_ok))
  39     # and place it into data_i.b
  40
  41     reg3_ok = yield dec2.e.read_reg3.ok
  42     reg1_ok = yield dec2.e.read_reg1.ok
  43     assert reg3_ok != reg1_ok
  44     if reg3_ok:
  45         data1 = yield dec2.e.read_reg3.data
  46         data1 = sim.gpr(data1).value
  47     elif reg1_ok:
  48         data1 = yield dec2.e.read_reg1.data
  49         data1 = sim.gpr(data1).value
  50     else:
  51         data1 = 0
  52
  53     yield alu.p.data_i.a.eq(data1)
  54
  55     # If there's an immediate, set the B operand to that
  56     reg2_ok = yield dec2.e.read_reg2.ok
  57     imm_ok = yield dec2.e.imm_data.imm_ok
  58     if imm_ok:
  59         data2 = yield dec2.e.imm_data.imm
  60     elif reg2_ok:
  61         data2 = yield dec2.e.read_reg2.data
  62         data2 = sim.gpr(data2).value
  63     else:
  64         data2 = 0
  65     yield alu.p.data_i.b.eq(data2)
  66
  67
  68
  69 def set_extra_alu_inputs(alu, dec2, sim):
  70     carry = 1 if sim.spr['XER'][XER_bits['CA']] else 0
  71     yield alu.p.data_i.carry_in.eq(carry)
  72     so = 1 if sim.spr['XER'][XER_bits['SO']] else 0
  73     yield alu.p.data_i.so.eq(so)
  74
  75
  76 # This test bench is a bit different than is usual. Initially when I
  77 # was writing it, I had all of the tests call a function to create a
  78 # device under test and simulator, initialize the dut, run the
  79 # simulation for ~2 cycles, and assert that the dut output what it
  80 # should have. However, this was really slow, since it needed to
  81 # create and tear down the dut and simulator for every test case.
  82
  83 # Now, instead of doing that, every test case in ALUTestCase puts some
  84 # data into the test_data list below, describing the instructions to
  85 # be tested and the initial state. Once all the tests have been run,
  86 # test_data gets passed to TestRunner which then sets up the DUT and
  87 # simulator once, runs all the data through it, and asserts that the
  88 # results match the pseudocode sim at every cycle.
  89
  90 # By doing this, I've reduced the time it takes to run the test suite
  91 # massively. Before, it took around 1 minute on my computer, now it
  92 # takes around 3 seconds
  93
  94 test_data = []
  95
  96
  97 class LogicalTestCase(FHDLTestCase):
  98     def __init__(self, name):
  99         super().__init__(name)
 100         self.test_name = name
 101     def run_tst_program(self, prog, initial_regs=[0] * 32, initial_sprs={}):
 102         tc = TestCase(prog, initial_regs, initial_sprs, self.test_name)
 103         test_data.append(tc)
 104
 105     def test_rand(self):
 106         insns = ["and", "or", "xor"]
 107         for i in range(40):
 108             choice = random.choice(insns)
 109             lst = [f"{choice} 3, 1, 2"]
 110             initial_regs = [0] * 32
 111             initial_regs[1] = random.randint(0, (1<<64)-1)
 112             initial_regs[2] = random.randint(0, (1<<64)-1)
 113             self.run_tst_program(Program(lst), initial_regs)
 114
 115     def test_rand_imm_logical(self):
 116         insns = ["andi.", "andis.", "ori", "oris", "xori", "xoris"]
 117         for i in range(10):
 118             choice = random.choice(insns)
 119             imm = random.randint(0, (1<<16)-1)
 120             lst = [f"{choice} 3, 1, {imm}"]
 121             print(lst)
 122             initial_regs = [0] * 32
 123             initial_regs[1] = random.randint(0, (1<<64)-1)
 124             self.run_tst_program(Program(lst), initial_regs)
 125
 126     def test_ilang(self):
 127         rec = CompALUOpSubset()
 128
 129         pspec = ALUPipeSpec(id_wid=2, op_wid=get_rec_width(rec))
 130         alu = LogicalBasePipe(pspec)
 131         vl = rtlil.convert(alu, ports=[])
 132         with open("logical_pipeline.il", "w") as f:
 133             f.write(vl)
 134
 135
 136 class TestRunner(FHDLTestCase):
 137     def __init__(self, test_data):
 138         super().__init__("run_all")
 139         self.test_data = test_data
 140
 141     def run_all(self):
 142         m = Module()
 143         comb = m.d.comb
 144         instruction = Signal(32)
 145
 146         pdecode = create_pdecode()
 147
 148         m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
 149
 150         rec = CompALUOpSubset()
 151
 152         pspec = ALUPipeSpec(id_wid=2, op_wid=get_rec_width(rec))
 153         m.submodules.alu = alu = LogicalBasePipe(pspec)
 154
 155         comb += alu.p.data_i.ctx.op.eq_from_execute1(pdecode2.e)
 156         comb += alu.p.valid_i.eq(1)
 157         comb += alu.n.ready_i.eq(1)
 158         comb += pdecode2.dec.raw_opcode_in.eq(instruction)
 159         sim = Simulator(m)
 160
 161         sim.add_clock(1e-6)
 162         def process():
 163             for test in self.test_data:
 164                 print(test.name)
 165                 program = test.program
 166                 self.subTest(test.name)
 167                 simulator = ISA(pdecode2, test.regs, test.sprs)
 168                 gen = program.generate_instructions()
 169                 instructions = list(zip(gen, program.assembly.splitlines()))
 170
 171                 index = simulator.pc.CIA.value//4
 172                 while index < len(instructions):
 173                     ins, code = instructions[index]
 174
 175                     print("0x{:X}".format(ins & 0xffffffff))
 176                     print(code)
 177
 178                     # ask the decoder to decode this binary data (endian'd)
 179                     yield pdecode2.dec.bigendian.eq(0)  # little / big?
 180                     yield instruction.eq(ins)          # raw binary instr.
 181                     yield Settle()
 182                     fn_unit = yield pdecode2.e.fn_unit
 183                     self.assertEqual(fn_unit, Function.LOGICAL.value)
 184                     yield from set_alu_inputs(alu, pdecode2, simulator)
 185                     yield from set_extra_alu_inputs(alu, pdecode2, simulator)
 186                     yield
 187                     opname = code.split(' ')[0]
 188                     yield from simulator.call(opname)
 189                     index = simulator.pc.CIA.value//4
 190
 191                     vld = yield alu.n.valid_o
 192                     while not vld:
 193                         yield
 194                         vld = yield alu.n.valid_o
 195                     yield
 196                     alu_out = yield alu.n.data_o.o
 197                     out_reg_valid = yield pdecode2.e.write_reg.ok
 198                     if out_reg_valid:
 199                         write_reg_idx = yield pdecode2.e.write_reg.data
 200                         expected = simulator.gpr(write_reg_idx).value
 201                         print(f"expected {expected:x}, actual: {alu_out:x}")
 202                         self.assertEqual(expected, alu_out)
 203                     yield from self.check_extra_alu_outputs(alu, pdecode2,
 204                                                             simulator)
 205
 206         sim.add_sync_process(process)
 207         with sim.write_vcd("simulator.vcd", "simulator.gtkw",
 208                             traces=[]):
 209             sim.run()
 210     def check_extra_alu_outputs(self, alu, dec2, sim):
 211         rc = yield dec2.e.rc.data
 212         if rc:
 213             cr_expected = sim.crl[0].get_range().value
 214             cr_actual = yield alu.n.data_o.cr0
 215             self.assertEqual(cr_expected, cr_actual)
 216
 217
 218 if __name__ == "__main__":
 219     unittest.main(exit=False)
 220     suite = unittest.TestSuite()
 221     suite.addTest(TestRunner(test_data))
 222
 223     runner = unittest.TextTestRunner()
 224     runner.run(suite)