46b27be73d2d60c9846aa78e54a2849b9e88c0e9
1 from nmigen
import Elaboratable
, Module
, Signal
, Array
4 class Reg_Rsv(Elaboratable
):
5 """ these are allocated per-Register (vertically),
6 and are each of length fu_count
8 def __init__(self
, fu_count
, n_src
, n_dest
):
11 self
.fu_count
= fu_count
12 self
.dest_rsel_i
= Array(Signal(fu_count
, name
="dst_rsel_i",
14 for i
in range(n_dest
))
15 self
.src_rsel_i
= Array(Signal(fu_count
, name
="src_rsel_i",
17 for i
in range(n_src
))
18 self
.dest_rsel_o
= Signal(n_dest
, reset_less
=True)
19 self
.src_rsel_o
= Signal(n_src
, reset_less
=True)
21 def elaborate(self
, platform
):
23 for i
in range(self
.n_dest
):
24 m
.d
.comb
+= self
.dest_rsel_o
[i
].eq(self
.dest_rsel_i
[i
].bool())
25 for i
in range(self
.n_src
):
26 m
.d
.comb
+= self
.src_rsel_o
[i
].eq(self
.src_rsel_i
[i
].bool())