291ecf0aaf7547089a3b4801812337cd949e66fc
[soc.git] / src / soc / shift_rot / pipe_data.py
1 from nmigen import Signal, Const
2 from nmutil.dynamicpipe import SimpleHandshakeRedir
3 from soc.alu.alu_input_record import CompALUOpSubset
4 from ieee754.fpcommon.getop import FPPipeContext
5
6
7 class IntegerData:
8
9 def __init__(self, pspec):
10 self.ctx = FPPipeContext(pspec)
11 self.muxid = self.ctx.muxid
12
13 def __iter__(self):
14 yield from self.ctx
15
16 def eq(self, i):
17 return [self.ctx.eq(i.ctx)]
18
19
20 class ShiftRotInputData(IntegerData):
21 def __init__(self, pspec):
22 super().__init__(pspec)
23 self.ra = Signal(64, reset_less=True) # RA
24 self.rs = Signal(64, reset_less=True) # RS
25 self.rb = Signal(64, reset_less=True) # RB/immediate
26 self.so = Signal(reset_less=True)
27 self.carry_in = Signal(reset_less=True)
28
29 def __iter__(self):
30 yield from super().__iter__()
31 yield self.ra
32 yield self.rs
33 yield self.rb
34 yield self.carry_in
35 yield self.so
36
37 def eq(self, i):
38 lst = super().eq(i)
39 return lst + [self.rs.eq(i.rs), self.ra.eq(i.ra),
40 self.rb.eq(i.rb),
41 self.carry_in.eq(i.carry_in),
42 self.so.eq(i.so)]