291ecf0aaf7547089a3b4801812337cd949e66fc
1 from nmigen
import Signal
, Const
2 from nmutil
.dynamicpipe
import SimpleHandshakeRedir
3 from soc
.alu
.alu_input_record
import CompALUOpSubset
4 from ieee754
.fpcommon
.getop
import FPPipeContext
9 def __init__(self
, pspec
):
10 self
.ctx
= FPPipeContext(pspec
)
11 self
.muxid
= self
.ctx
.muxid
17 return [self
.ctx
.eq(i
.ctx
)]
20 class ShiftRotInputData(IntegerData
):
21 def __init__(self
, pspec
):
22 super().__init
__(pspec
)
23 self
.ra
= Signal(64, reset_less
=True) # RA
24 self
.rs
= Signal(64, reset_less
=True) # RS
25 self
.rb
= Signal(64, reset_less
=True) # RB/immediate
26 self
.so
= Signal(reset_less
=True)
27 self
.carry_in
= Signal(reset_less
=True)
30 yield from super().__iter
__()
39 return lst
+ [self
.rs
.eq(i
.rs
), self
.ra
.eq(i
.ra
),
41 self
.carry_in
.eq(i
.carry_in
),