0756e4b68b383586b1c1479a20e031d898a7fd07
3 not in any way intended for production use. this runs a FSM that:
5 * reads the Program Counter from StateRegs
6 * reads an instruction from a fixed-size Test Memory
7 * issues it to the Simple Core
8 * waits for it to complete
10 * does it all over again
12 the purpose of this module is to verify the functional correctness
13 of the Function Units in the absolute simplest and clearest possible
14 way, and to at provide something that can be further incrementally
18 from nmigen
import (Elaboratable
, Module
, Signal
, ClockSignal
, ResetSignal
,
19 ClockDomain
, DomainRenamer
, Mux
, Const
, Repl
, Cat
)
20 from nmigen
.cli
import rtlil
21 from nmigen
.cli
import main
24 from nmutil
.singlepipe
import ControlBase
25 from soc
.simple
.core_data
import FetchOutput
, FetchInput
27 from nmigen
.lib
.coding
import PriorityEncoder
29 from openpower
.decoder
.power_decoder
import create_pdecode
30 from openpower
.decoder
.power_decoder2
import PowerDecode2
, SVP64PrefixDecoder
31 from openpower
.decoder
.decode2execute1
import IssuerDecode2ToOperand
32 from openpower
.decoder
.decode2execute1
import Data
33 from openpower
.decoder
.power_enums
import (MicrOp
, SVP64PredInt
, SVP64PredCR
,
35 from openpower
.state
import CoreState
36 from openpower
.consts
import (CR
, SVP64CROffs
, MSR
)
37 from soc
.experiment
.testmem
import TestMemory
# test only for instructions
38 from soc
.regfile
.regfiles
import StateRegs
, FastRegs
39 from soc
.simple
.core
import NonProductionCore
40 from soc
.config
.test
.test_loadstore
import TestMemPspec
41 from soc
.config
.ifetch
import ConfigFetchUnit
42 from soc
.debug
.dmi
import CoreDebug
, DMIInterface
43 from soc
.debug
.jtag
import JTAG
44 from soc
.config
.pinouts
import get_pinspecs
45 from soc
.interrupts
.xics
import XICS_ICP
, XICS_ICS
46 from soc
.bus
.simple_gpio
import SimpleGPIO
47 from soc
.bus
.SPBlock512W64B8W
import SPBlock512W64B8W
48 from soc
.clock
.select
import ClockSelect
49 from soc
.clock
.dummypll
import DummyPLL
50 from openpower
.sv
.svstate
import SVSTATERec
51 from soc
.experiment
.icache
import ICache
53 from nmutil
.util
import rising_edge
56 def get_insn(f_instr_o
, pc
):
57 if f_instr_o
.width
== 32:
60 # 64-bit: bit 2 of pc decides which word to select
61 return f_instr_o
.word_select(pc
[2], 32)
63 # gets state input or reads from state regfile
66 def state_get(m
, res
, core_rst
, state_i
, name
, regfile
, regnum
):
69 # read the {insert state variable here}
70 res_ok_delay
= Signal(name
="%s_ok_delay" % name
)
72 sync
+= res_ok_delay
.eq(~state_i
.ok
)
73 with m
.If(state_i
.ok
):
74 # incoming override (start from pc_i)
75 comb
+= res
.eq(state_i
.data
)
77 # otherwise read StateRegs regfile for {insert state here}...
78 comb
+= regfile
.ren
.eq(1 << regnum
)
79 # ... but on a 1-clock delay
80 with m
.If(res_ok_delay
):
81 comb
+= res
.eq(regfile
.o_data
)
84 def get_predint(m
, mask
, name
):
85 """decode SVP64 predicate integer mask field to reg number and invert
86 this is identical to the equivalent function in ISACaller except that
87 it doesn't read the INT directly, it just decodes "what needs to be done"
88 i.e. which INT reg, whether it is shifted and whether it is bit-inverted.
90 * all1s is set to indicate that no mask is to be applied.
91 * regread indicates the GPR register number to be read
92 * invert is set to indicate that the register value is to be inverted
93 * unary indicates that the contents of the register is to be shifted 1<<r3
96 regread
= Signal(5, name
=name
+"regread")
97 invert
= Signal(name
=name
+"invert")
98 unary
= Signal(name
=name
+"unary")
99 all1s
= Signal(name
=name
+"all1s")
101 with m
.Case(SVP64PredInt
.ALWAYS
.value
):
102 comb
+= all1s
.eq(1) # use 0b1111 (all ones)
103 with m
.Case(SVP64PredInt
.R3_UNARY
.value
):
104 comb
+= regread
.eq(3)
105 comb
+= unary
.eq(1) # 1<<r3 - shift r3 (single bit)
106 with m
.Case(SVP64PredInt
.R3
.value
):
107 comb
+= regread
.eq(3)
108 with m
.Case(SVP64PredInt
.R3_N
.value
):
109 comb
+= regread
.eq(3)
111 with m
.Case(SVP64PredInt
.R10
.value
):
112 comb
+= regread
.eq(10)
113 with m
.Case(SVP64PredInt
.R10_N
.value
):
114 comb
+= regread
.eq(10)
116 with m
.Case(SVP64PredInt
.R30
.value
):
117 comb
+= regread
.eq(30)
118 with m
.Case(SVP64PredInt
.R30_N
.value
):
119 comb
+= regread
.eq(30)
121 return regread
, invert
, unary
, all1s
124 def get_predcr(m
, mask
, name
):
125 """decode SVP64 predicate CR to reg number field and invert status
126 this is identical to _get_predcr in ISACaller
129 idx
= Signal(2, name
=name
+"idx")
130 invert
= Signal(name
=name
+"crinvert")
132 with m
.Case(SVP64PredCR
.LT
.value
):
133 comb
+= idx
.eq(CR
.LT
)
135 with m
.Case(SVP64PredCR
.GE
.value
):
136 comb
+= idx
.eq(CR
.LT
)
138 with m
.Case(SVP64PredCR
.GT
.value
):
139 comb
+= idx
.eq(CR
.GT
)
141 with m
.Case(SVP64PredCR
.LE
.value
):
142 comb
+= idx
.eq(CR
.GT
)
144 with m
.Case(SVP64PredCR
.EQ
.value
):
145 comb
+= idx
.eq(CR
.EQ
)
147 with m
.Case(SVP64PredCR
.NE
.value
):
148 comb
+= idx
.eq(CR
.EQ
)
150 with m
.Case(SVP64PredCR
.SO
.value
):
151 comb
+= idx
.eq(CR
.SO
)
153 with m
.Case(SVP64PredCR
.NS
.value
):
154 comb
+= idx
.eq(CR
.SO
)
159 class TestIssuerBase(Elaboratable
):
160 """TestIssuerBase - common base class for Issuers
162 takes care of power-on reset, peripherals, debug, DEC/TB,
163 and gets PC/MSR/SVSTATE from the State Regfile etc.
166 def __init__(self
, pspec
):
168 # test if microwatt compatibility is to be enabled
169 self
.microwatt_compat
= (hasattr(pspec
, "microwatt_compat") and
170 (pspec
.microwatt_compat
== True))
171 self
.alt_reset
= Signal(reset_less
=True) # not connected yet (microwatt)
173 if self
.microwatt_compat
:
175 if hasattr(pspec
, "microwatt_old"):
176 self
.microwatt_old
= pspec
.microwatt_old
178 self
.microwatt_old
= True # PLEASE DO NOT ALTER THIS
180 if hasattr(pspec
, "microwatt_debug"):
181 self
.microwatt_debug
= pspec
.microwatt_debug
183 self
.microwatt_debug
= True # set to False when using an FPGA
185 # test is SVP64 is to be enabled
186 self
.svp64_en
= hasattr(pspec
, "svp64") and (pspec
.svp64
== True)
188 # and if regfiles are reduced
189 self
.regreduce_en
= (hasattr(pspec
, "regreduce") and
190 (pspec
.regreduce
== True))
192 # and if overlap requested
193 self
.allow_overlap
= (hasattr(pspec
, "allow_overlap") and
194 (pspec
.allow_overlap
== True))
196 # and get the core domain
197 self
.core_domain
= "coresync"
198 if (hasattr(pspec
, "core_domain") and
199 isinstance(pspec
.core_domain
, str)):
200 self
.core_domain
= pspec
.core_domain
202 # JTAG interface. add this right at the start because if it's
203 # added it *modifies* the pspec, by adding enable/disable signals
204 # for parts of the rest of the core
205 self
.jtag_en
= hasattr(pspec
, "debug") and pspec
.debug
== 'jtag'
206 #self.dbg_domain = "sync" # sigh "dbgsunc" too problematic
207 self
.dbg_domain
= "dbgsync" # domain for DMI/JTAG clock
209 # XXX MUST keep this up-to-date with litex, and
210 # soc-cocotb-sim, and err.. all needs sorting out, argh
213 'eint', 'gpio', 'mspi0',
214 # 'mspi1', - disabled for now
215 # 'pwm', 'sd0', - disabled for now
217 self
.jtag
= JTAG(get_pinspecs(subset
=subset
),
218 domain
=self
.dbg_domain
)
219 # add signals to pspec to enable/disable icache and dcache
220 # (or data and intstruction wishbone if icache/dcache not included)
221 # https://bugs.libre-soc.org/show_bug.cgi?id=520
222 # TODO: do we actually care if these are not domain-synchronised?
223 # honestly probably not.
224 pspec
.wb_icache_en
= self
.jtag
.wb_icache_en
225 pspec
.wb_dcache_en
= self
.jtag
.wb_dcache_en
226 self
.wb_sram_en
= self
.jtag
.wb_sram_en
228 self
.wb_sram_en
= Const(1)
230 # add 4k sram blocks?
231 self
.sram4x4k
= (hasattr(pspec
, "sram4x4kblock") and
232 pspec
.sram4x4kblock
== True)
236 self
.sram4k
.append(SPBlock512W64B8W(name
="sram4k_%d" % i
,
240 # add interrupt controller?
241 self
.xics
= hasattr(pspec
, "xics") and pspec
.xics
== True
243 self
.xics_icp
= XICS_ICP()
244 self
.xics_ics
= XICS_ICS()
245 self
.int_level_i
= self
.xics_ics
.int_level_i
247 self
.ext_irq
= Signal()
249 # add GPIO peripheral?
250 self
.gpio
= hasattr(pspec
, "gpio") and pspec
.gpio
== True
252 self
.simple_gpio
= SimpleGPIO()
253 self
.gpio_o
= self
.simple_gpio
.gpio_o
255 # main instruction core. suitable for prototyping / demo only
256 self
.core
= core
= NonProductionCore(pspec
)
257 self
.core_rst
= ResetSignal(self
.core_domain
)
259 # instruction decoder. goes into Trap Record
260 #pdecode = create_pdecode()
261 self
.cur_state
= CoreState("cur") # current state (MSR/PC/SVSTATE)
262 self
.pdecode2
= PowerDecode2(None, state
=self
.cur_state
,
263 opkls
=IssuerDecode2ToOperand
,
264 svp64_en
=self
.svp64_en
,
265 regreduce_en
=self
.regreduce_en
)
266 pdecode
= self
.pdecode2
.dec
269 self
.svp64
= SVP64PrefixDecoder() # for decoding SVP64 prefix
271 self
.update_svstate
= Signal() # set this if updating svstate
272 self
.new_svstate
= new_svstate
= SVSTATERec("new_svstate")
274 # Test Instruction memory
275 if hasattr(core
, "icache"):
276 # XXX BLECH! use pspec to transfer the I-Cache to ConfigFetchUnit
277 # truly dreadful. needs a huge reorg.
278 pspec
.icache
= core
.icache
279 self
.imem
= ConfigFetchUnit(pspec
).fu
282 self
.dbg
= CoreDebug()
283 self
.dbg_rst_i
= Signal(reset_less
=True)
285 # instruction go/monitor
286 self
.pc_o
= Signal(64, reset_less
=True)
287 self
.pc_i
= Data(64, "pc_i") # set "ok" to indicate "please change me"
288 self
.msr_i
= Data(64, "msr_i") # set "ok" to indicate "please change me"
289 self
.svstate_i
= Data(64, "svstate_i") # ditto
290 self
.core_bigendian_i
= Signal() # TODO: set based on MSR.LE
291 self
.busy_o
= Signal(reset_less
=True)
292 self
.memerr_o
= Signal(reset_less
=True)
294 # STATE regfile read /write ports for PC, MSR, SVSTATE
295 staterf
= self
.core
.regs
.rf
['state']
296 self
.state_r_msr
= staterf
.r_ports
['msr'] # MSR rd
297 self
.state_r_pc
= staterf
.r_ports
['cia'] # PC rd
298 self
.state_r_sv
= staterf
.r_ports
['sv'] # SVSTATE rd
300 self
.state_w_msr
= staterf
.w_ports
['d_wr2'] # MSR wr
301 self
.state_w_pc
= staterf
.w_ports
['d_wr1'] # PC wr
302 self
.state_w_sv
= staterf
.w_ports
['sv'] # SVSTATE wr
304 # DMI interface access
305 intrf
= self
.core
.regs
.rf
['int']
306 fastrf
= self
.core
.regs
.rf
['fast']
307 crrf
= self
.core
.regs
.rf
['cr']
308 xerrf
= self
.core
.regs
.rf
['xer']
309 self
.int_r
= intrf
.r_ports
['dmi'] # INT DMI read
310 self
.cr_r
= crrf
.r_ports
['full_cr_dbg'] # CR DMI read
311 self
.xer_r
= xerrf
.r_ports
['full_xer'] # XER DMI read
312 self
.fast_r
= fastrf
.r_ports
['dmi'] # FAST DMI read
316 self
.int_pred
= intrf
.r_ports
['pred'] # INT predicate read
317 self
.cr_pred
= crrf
.r_ports
['cr_pred'] # CR predicate read
319 # hack method of keeping an eye on whether branch/trap set the PC
320 self
.state_nia
= self
.core
.regs
.rf
['state'].w_ports
['nia']
321 self
.state_nia
.wen
.name
= 'state_nia_wen'
322 # and whether SPR pipeline sets DEC or TB
323 self
.state_spr
= self
.core
.regs
.rf
['state'].w_ports
['state1']
325 # pulse to synchronize the simulator at instruction end
326 self
.insn_done
= Signal()
328 # indicate any instruction still outstanding, in execution
329 self
.any_busy
= Signal()
332 # store copies of predicate masks
333 self
.srcmask
= Signal(64)
334 self
.dstmask
= Signal(64)
336 # sigh, the wishbone addresses are not wishbone-compliant
337 # in old versions of microwatt, tplaten_3d_game is a new one
338 if self
.microwatt_compat
:
339 self
.ibus_adr
= Signal(32, name
='wishbone_insn_out.adr')
340 self
.dbus_adr
= Signal(32, name
='wishbone_data_out.adr')
342 # add an output of the PC and instruction, and whether it was requested
343 # this is for verilator debug purposes
344 if self
.microwatt_compat
:
345 self
.nia
= Signal(64)
346 self
.msr_o
= Signal(64)
347 self
.nia_req
= Signal(1)
348 self
.insn
= Signal(32)
349 self
.ldst_req
= Signal(1)
350 self
.ldst_addr
= Signal(1)
352 # for pausing dec/tb during an SPR pipeline event, this
353 # ensures that an SPR write (mtspr) to TB or DEC does not
354 # get overwritten by the DEC/TB FSM
355 self
.pause_dec_tb
= Signal()
357 def setup_peripherals(self
, m
):
358 comb
, sync
= m
.d
.comb
, m
.d
.sync
360 # okaaaay so the debug module must be in coresync clock domain
361 # but NOT its reset signal. to cope with this, set every single
362 # submodule explicitly in coresync domain, debug and JTAG
363 # in their own one but using *external* reset.
364 csd
= DomainRenamer(self
.core_domain
)
365 dbd
= DomainRenamer(self
.dbg_domain
)
367 if self
.microwatt_compat
:
368 m
.submodules
.core
= core
= self
.core
370 m
.submodules
.core
= core
= csd(self
.core
)
372 # this _so_ needs sorting out. ICache is added down inside
373 # LoadStore1 and is already a submodule of LoadStore1
374 if not isinstance(self
.imem
, ICache
):
375 m
.submodules
.imem
= imem
= csd(self
.imem
)
377 # set up JTAG Debug Module (in correct domain)
378 m
.submodules
.dbg
= dbg
= dbd(self
.dbg
)
380 m
.submodules
.jtag
= jtag
= dbd(self
.jtag
)
381 # TODO: UART2GDB mux, here, from external pin
382 # see https://bugs.libre-soc.org/show_bug.cgi?id=499
383 sync
+= dbg
.dmi
.connect_to(jtag
.dmi
)
385 # fixup the clocks in microwatt-compat mode (but leave resets alone
386 # so that microwatt soc.vhdl can pull a reset on the core or DMI
387 # can do it, just like in TestIssuer)
388 if self
.microwatt_compat
:
389 intclk
= ClockSignal(self
.core_domain
)
390 dbgclk
= ClockSignal(self
.dbg_domain
)
391 if self
.core_domain
!= 'sync':
392 comb
+= intclk
.eq(ClockSignal())
393 if self
.dbg_domain
!= 'sync':
394 comb
+= dbgclk
.eq(ClockSignal())
396 # if using old version of microwatt
397 # drop the first 3 bits of the incoming wishbone addresses
398 if self
.microwatt_compat
:
399 ibus
= self
.imem
.ibus
400 dbus
= self
.core
.l0
.cmpi
.wb_bus()
401 if self
.microwatt_old
:
402 comb
+= self
.ibus_adr
.eq(Cat(Const(0, 3), ibus
.adr
))
403 comb
+= self
.dbus_adr
.eq(Cat(Const(0, 3), dbus
.adr
))
405 comb
+= self
.ibus_adr
.eq(ibus
.adr
)
406 comb
+= self
.dbus_adr
.eq(dbus
.adr
)
407 if self
.microwatt_debug
:
408 # microwatt verilator debug purposes
409 pi
= self
.core
.l0
.cmpi
.pi
.pi
410 comb
+= self
.ldst_req
.eq(pi
.addr_ok_o
)
411 comb
+= self
.ldst_addr
.eq(pi
.addr
)
413 cur_state
= self
.cur_state
415 # 4x 4k SRAM blocks. these simply "exist", they get routed in litex
417 for i
, sram
in enumerate(self
.sram4k
):
418 m
.submodules
["sram4k_%d" % i
] = csd(sram
)
419 comb
+= sram
.enable
.eq(self
.wb_sram_en
)
421 # XICS interrupt handler
423 m
.submodules
.xics_icp
= icp
= csd(self
.xics_icp
)
424 m
.submodules
.xics_ics
= ics
= csd(self
.xics_ics
)
425 comb
+= icp
.ics_i
.eq(ics
.icp_o
) # connect ICS to ICP
426 sync
+= cur_state
.eint
.eq(icp
.core_irq_o
) # connect ICP to core
428 sync
+= cur_state
.eint
.eq(self
.ext_irq
) # connect externally
430 # GPIO test peripheral
432 m
.submodules
.simple_gpio
= simple_gpio
= csd(self
.simple_gpio
)
434 # connect one GPIO output to ICS bit 15 (like in microwatt soc.vhdl)
435 # XXX causes litex ECP5 test to get wrong idea about input and output
436 # (but works with verilator sim *sigh*)
437 # if self.gpio and self.xics:
438 # comb += self.int_level_i[15].eq(simple_gpio.gpio_o[0])
440 # instruction decoder
441 pdecode
= create_pdecode()
442 m
.submodules
.dec2
= pdecode2
= csd(self
.pdecode2
)
444 m
.submodules
.svp64
= svp64
= csd(self
.svp64
)
446 # clock delay power-on reset
447 cd_por
= ClockDomain(reset_less
=True)
448 cd_sync
= ClockDomain()
449 m
.domains
+= cd_por
, cd_sync
450 core_sync
= ClockDomain(self
.core_domain
)
451 if self
.core_domain
!= "sync":
452 m
.domains
+= core_sync
453 if self
.dbg_domain
!= "sync":
454 dbg_sync
= ClockDomain(self
.dbg_domain
)
455 m
.domains
+= dbg_sync
457 # create a delay, but remember it is in the power-on-reset clock domain!
458 ti_rst
= Signal(reset_less
=True)
459 delay
= Signal(range(4), reset
=3)
460 stop_delay
= Signal(range(16), reset
=5)
461 with m
.If(delay
!= 0):
462 m
.d
.por
+= delay
.eq(delay
- 1) # decrement... in POR domain!
463 with m
.If(stop_delay
!= 0):
464 m
.d
.por
+= stop_delay
.eq(stop_delay
- 1) # likewise
465 comb
+= cd_por
.clk
.eq(ClockSignal())
467 # power-on reset delay
468 core_rst
= ResetSignal(self
.core_domain
)
469 if self
.core_domain
!= "sync":
470 comb
+= ti_rst
.eq(delay
!= 0 | dbg
.core_rst_o |
ResetSignal())
471 comb
+= core_rst
.eq(ti_rst
)
473 with m
.If(delay
!= 0 | dbg
.core_rst_o
):
474 comb
+= core_rst
.eq(1)
475 with m
.If(stop_delay
!= 0):
476 # run DMI core-stop as well but on an extra couple of cycles
477 comb
+= dbg
.core_stopped_i
.eq(1)
479 # connect external reset signal to DMI Reset
480 if self
.dbg_domain
!= "sync":
481 dbg_rst
= ResetSignal(self
.dbg_domain
)
482 comb
+= dbg_rst
.eq(self
.dbg_rst_i
)
484 # busy/halted signals from core
485 core_busy_o
= ~core
.p
.o_ready | core
.n
.o_data
.busy_o
# core is busy
486 comb
+= self
.busy_o
.eq(core_busy_o
)
487 comb
+= pdecode2
.dec
.bigendian
.eq(self
.core_bigendian_i
)
489 # temporary hack: says "go" immediately for both address gen and ST
490 # XXX: st.go_i is set to 1 cycle delay to reduce combinatorial chains
492 ldst
= core
.fus
.fus
['ldst0']
493 st_go_edge
= rising_edge(m
, ldst
.st
.rel_o
)
494 # link addr-go direct to rel
495 m
.d
.comb
+= ldst
.ad
.go_i
.eq(ldst
.ad
.rel_o
)
496 m
.d
.sync
+= ldst
.st
.go_i
.eq(st_go_edge
) # link store-go to rising rel
498 def do_dmi(self
, m
, dbg
):
499 """deals with DMI debug requests
501 currently only provides read requests for the INT regfile, CR and XER
502 it will later also deal with *writing* to these regfiles.
506 dmi
, d_reg
, d_cr
, d_xer
, = dbg
.dmi
, dbg
.d_gpr
, dbg
.d_cr
, dbg
.d_xer
508 intrf
= self
.core
.regs
.rf
['int']
509 fastrf
= self
.core
.regs
.rf
['fast']
511 with m
.If(d_reg
.req
): # request for regfile access being made
512 # TODO: error-check this
513 # XXX should this be combinatorial? sync better?
515 comb
+= self
.int_r
.ren
.eq(1 << d_reg
.addr
)
517 comb
+= self
.int_r
.addr
.eq(d_reg
.addr
)
518 comb
+= self
.int_r
.ren
.eq(1)
519 d_reg_delay
= Signal()
520 sync
+= d_reg_delay
.eq(d_reg
.req
)
521 with m
.If(d_reg_delay
):
522 # data arrives one clock later
523 comb
+= d_reg
.data
.eq(self
.int_r
.o_data
)
524 comb
+= d_reg
.ack
.eq(1)
527 with m
.If(d_fast
.req
): # request for regfile access being made
529 comb
+= self
.fast_r
.ren
.eq(1 << d_fast
.addr
)
531 comb
+= self
.fast_r
.addr
.eq(d_fast
.addr
)
532 comb
+= self
.fast_r
.ren
.eq(1)
533 d_fast_delay
= Signal()
534 sync
+= d_fast_delay
.eq(d_fast
.req
)
535 with m
.If(d_fast_delay
):
536 # data arrives one clock later
537 comb
+= d_fast
.data
.eq(self
.fast_r
.o_data
)
538 comb
+= d_fast
.ack
.eq(1)
540 # sigh same thing for CR debug
541 with m
.If(d_cr
.req
): # request for regfile access being made
542 comb
+= self
.cr_r
.ren
.eq(0b11111111) # enable all
543 d_cr_delay
= Signal()
544 sync
+= d_cr_delay
.eq(d_cr
.req
)
545 with m
.If(d_cr_delay
):
546 # data arrives one clock later
547 comb
+= d_cr
.data
.eq(self
.cr_r
.o_data
)
548 comb
+= d_cr
.ack
.eq(1)
551 with m
.If(d_xer
.req
): # request for regfile access being made
552 comb
+= self
.xer_r
.ren
.eq(0b111111) # enable all
553 d_xer_delay
= Signal()
554 sync
+= d_xer_delay
.eq(d_xer
.req
)
555 with m
.If(d_xer_delay
):
556 # data arrives one clock later
557 comb
+= d_xer
.data
.eq(self
.xer_r
.o_data
)
558 comb
+= d_xer
.ack
.eq(1)
560 def tb_dec_fsm(self
, m
, spr_dec
):
563 this is a FSM for updating either dec or tb. it runs alternately
564 DEC, TB, DEC, TB. note that SPR pipeline could have written a new
565 value to DEC, however the regfile has "passthrough" on it so this
568 see v3.0B p1097-1099 for Timer Resource and p1065 and p1076
571 comb
, sync
= m
.d
.comb
, m
.d
.sync
572 state_rf
= self
.core
.regs
.rf
['state']
573 state_r_dectb
= state_rf
.r_ports
['issue'] # DEC/TB
574 state_w_dectb
= state_rf
.w_ports
['issue'] # DEC/TB
578 # initiates read of current DEC
579 with m
.State("DEC_READ"):
580 comb
+= state_r_dectb
.ren
.eq(1<<StateRegs
.DEC
)
581 with m
.If(~self
.pause_dec_tb
):
584 # waits for DEC read to arrive (1 cycle), updates with new value
585 # respects if dec/tb writing has been paused
586 with m
.State("DEC_WRITE"):
587 with m
.If(self
.pause_dec_tb
):
588 # if paused, return to reading
592 # TODO: MSR.LPCR 32-bit decrement mode
593 comb
+= new_dec
.eq(state_r_dectb
.o_data
- 1)
594 comb
+= state_w_dectb
.wen
.eq(1<<StateRegs
.DEC
)
595 comb
+= state_w_dectb
.i_data
.eq(new_dec
)
596 # copy to cur_state for decoder, for an interrupt
597 sync
+= spr_dec
.eq(new_dec
)
600 # initiates read of current TB
601 with m
.State("TB_READ"):
602 comb
+= state_r_dectb
.ren
.eq(1<<StateRegs
.TB
)
603 with m
.If(~self
.pause_dec_tb
):
606 # waits for read TB to arrive, initiates write of current TB
607 # respects if dec/tb writing has been paused
608 with m
.State("TB_WRITE"):
609 with m
.If(self
.pause_dec_tb
):
610 # if paused, return to reading
614 comb
+= new_tb
.eq(state_r_dectb
.o_data
+ 1)
615 comb
+= state_w_dectb
.wen
.eq(1<<StateRegs
.TB
)
616 comb
+= state_w_dectb
.i_data
.eq(new_tb
)
621 def elaborate(self
, platform
):
624 comb
, sync
= m
.d
.comb
, m
.d
.sync
625 cur_state
= self
.cur_state
626 pdecode2
= self
.pdecode2
629 # set up peripherals and core
630 core_rst
= self
.core_rst
631 self
.setup_peripherals(m
)
633 # reset current state if core reset requested
635 m
.d
.sync
+= self
.cur_state
.eq(0)
636 # and, sigh, set configured values, which are also done in regfile
637 # XXX ??? what the hell is the shift for??
638 m
.d
.sync
+= self
.cur_state
.pc
.eq(self
.core
.pc_at_reset
)
639 m
.d
.sync
+= self
.cur_state
.msr
.eq(self
.core
.msr_at_reset
)
641 # check halted condition: requested PC to execute matches DMI stop addr
642 # and immediately stop. address of 0xffff_ffff_ffff_ffff can never
645 comb
+= halted
.eq(dbg
.stop_addr_o
== dbg
.state
.pc
)
647 comb
+= dbg
.core_stopped_i
.eq(1)
648 comb
+= dbg
.terminate_i
.eq(1)
650 # PC and instruction from I-Memory
651 comb
+= self
.pc_o
.eq(cur_state
.pc
)
652 self
.pc_changed
= Signal() # note write to PC
653 self
.msr_changed
= Signal() # note write to MSR
654 self
.sv_changed
= Signal() # note write to SVSTATE
656 # read state either from incoming override or from regfile
657 state
= CoreState("get") # current state (MSR/PC/SVSTATE)
658 state_get(m
, state
.msr
, core_rst
, self
.msr_i
,
660 self
.state_r_msr
, StateRegs
.MSR
)
661 state_get(m
, state
.pc
, core_rst
, self
.pc_i
,
663 self
.state_r_pc
, StateRegs
.PC
)
664 state_get(m
, state
.svstate
, core_rst
, self
.svstate_i
,
665 "svstate", # read SVSTATE
666 self
.state_r_sv
, StateRegs
.SVSTATE
)
668 # don't write pc every cycle
669 comb
+= self
.state_w_pc
.wen
.eq(0)
670 comb
+= self
.state_w_pc
.i_data
.eq(0)
672 # connect up debug state. note "combinatorially same" below,
673 # this is a bit naff, passing state over in the dbg class, but
674 # because it is combinatorial it achieves the desired goal
675 comb
+= dbg
.state
.eq(state
)
677 # this bit doesn't have to be in the FSM: connect up to read
678 # regfiles on demand from DMI
681 # DEC and TB inc/dec FSM. copy of DEC is put into CoreState,
682 # (which uses that in PowerDecoder2 to raise 0x900 exception)
683 self
.tb_dec_fsm(m
, cur_state
.dec
)
685 # while stopped, allow updating the MSR, PC and SVSTATE.
686 # these are mainly for debugging purposes (including DMI/JTAG)
687 with m
.If(dbg
.core_stopped_i
):
688 with m
.If(self
.pc_i
.ok
):
689 comb
+= self
.state_w_pc
.wen
.eq(1 << StateRegs
.PC
)
690 comb
+= self
.state_w_pc
.i_data
.eq(self
.pc_i
.data
)
691 sync
+= self
.pc_changed
.eq(1)
692 with m
.If(self
.msr_i
.ok
):
693 comb
+= self
.state_w_msr
.wen
.eq(1 << StateRegs
.MSR
)
694 comb
+= self
.state_w_msr
.i_data
.eq(self
.msr_i
.data
)
695 sync
+= self
.msr_changed
.eq(1)
696 with m
.If(self
.svstate_i
.ok | self
.update_svstate
):
697 with m
.If(self
.svstate_i
.ok
): # over-ride from external source
698 comb
+= self
.new_svstate
.eq(self
.svstate_i
.data
)
699 comb
+= self
.state_w_sv
.wen
.eq(1 << StateRegs
.SVSTATE
)
700 comb
+= self
.state_w_sv
.i_data
.eq(self
.new_svstate
)
701 sync
+= self
.sv_changed
.eq(1)
703 # start renaming some of the ports to match microwatt
704 if self
.microwatt_compat
:
705 self
.core
.o
.core_terminate_o
.name
= "terminated_out"
706 # names of DMI interface
707 self
.dbg
.dmi
.addr_i
.name
= 'dmi_addr'
708 self
.dbg
.dmi
.din
.name
= 'dmi_din'
709 self
.dbg
.dmi
.dout
.name
= 'dmi_dout'
710 self
.dbg
.dmi
.req_i
.name
= 'dmi_req'
711 self
.dbg
.dmi
.we_i
.name
= 'dmi_wr'
712 self
.dbg
.dmi
.ack_o
.name
= 'dmi_ack'
713 # wishbone instruction bus
714 ibus
= self
.imem
.ibus
715 ibus
.adr
.name
= 'wishbone_insn_out.adr'
716 ibus
.dat_w
.name
= 'wishbone_insn_out.dat'
717 ibus
.sel
.name
= 'wishbone_insn_out.sel'
718 ibus
.cyc
.name
= 'wishbone_insn_out.cyc'
719 ibus
.stb
.name
= 'wishbone_insn_out.stb'
720 ibus
.we
.name
= 'wishbone_insn_out.we'
721 ibus
.dat_r
.name
= 'wishbone_insn_in.dat'
722 ibus
.ack
.name
= 'wishbone_insn_in.ack'
723 ibus
.stall
.name
= 'wishbone_insn_in.stall'
725 dbus
= self
.core
.l0
.cmpi
.wb_bus()
726 dbus
.adr
.name
= 'wishbone_data_out.adr'
727 dbus
.dat_w
.name
= 'wishbone_data_out.dat'
728 dbus
.sel
.name
= 'wishbone_data_out.sel'
729 dbus
.cyc
.name
= 'wishbone_data_out.cyc'
730 dbus
.stb
.name
= 'wishbone_data_out.stb'
731 dbus
.we
.name
= 'wishbone_data_out.we'
732 dbus
.dat_r
.name
= 'wishbone_data_in.dat'
733 dbus
.ack
.name
= 'wishbone_data_in.ack'
734 dbus
.stall
.name
= 'wishbone_data_in.stall'
739 yield from self
.pc_i
.ports()
740 yield from self
.msr_i
.ports()
743 yield from self
.core
.ports()
744 yield from self
.imem
.ports()
745 yield self
.core_bigendian_i
751 def external_ports(self
):
752 if self
.microwatt_compat
:
753 ports
= [self
.core
.o
.core_terminate_o
,
755 self
.alt_reset
, # not connected yet
756 self
.nia
, self
.insn
, self
.nia_req
, self
.msr_o
,
757 self
.ldst_req
, self
.ldst_addr
,
761 ports
+= list(self
.dbg
.dmi
.ports())
762 # for dbus/ibus microwatt, exclude err btw and cti
763 for name
, sig
in self
.imem
.ibus
.fields
.items():
764 if name
not in ['err', 'bte', 'cti', 'adr']:
766 for name
, sig
in self
.core
.l0
.cmpi
.wb_bus().fields
.items():
767 if name
not in ['err', 'bte', 'cti', 'adr']:
769 # microwatt non-compliant with wishbone
770 ports
.append(self
.ibus_adr
)
771 ports
.append(self
.dbus_adr
)
774 ports
= self
.pc_i
.ports()
775 ports
= self
.msr_i
.ports()
776 ports
+= [self
.pc_o
, self
.memerr_o
, self
.core_bigendian_i
, self
.busy_o
,
780 ports
+= list(self
.jtag
.external_ports())
782 # don't add DMI if JTAG is enabled
783 ports
+= list(self
.dbg
.dmi
.ports())
785 ports
+= list(self
.imem
.ibus
.fields
.values())
786 ports
+= list(self
.core
.l0
.cmpi
.wb_bus().fields
.values())
789 for sram
in self
.sram4k
:
790 ports
+= list(sram
.bus
.fields
.values())
793 ports
+= list(self
.xics_icp
.bus
.fields
.values())
794 ports
+= list(self
.xics_ics
.bus
.fields
.values())
795 ports
.append(self
.int_level_i
)
797 ports
.append(self
.ext_irq
)
800 ports
+= list(self
.simple_gpio
.bus
.fields
.values())
801 ports
.append(self
.gpio_o
)
809 class TestIssuerInternal(TestIssuerBase
):
810 """TestIssuer - reads instructions from TestMemory and issues them
812 efficiency and speed is not the main goal here: functional correctness
813 and code clarity is. optimisations (which almost 100% interfere with
814 easy understanding) come later.
817 def fetch_fsm(self
, m
, dbg
, core
, core_rst
, nia
, is_svp64_mode
,
818 fetch_pc_o_ready
, fetch_pc_i_valid
,
819 fetch_insn_o_valid
, fetch_insn_i_ready
):
822 this FSM performs fetch of raw instruction data, partial-decodes
823 it 32-bit at a time to detect SVP64 prefixes, and will optionally
824 read a 2nd 32-bit quantity if that occurs.
828 pdecode2
= self
.pdecode2
829 cur_state
= self
.cur_state
830 dec_opcode_i
= pdecode2
.dec
.raw_opcode_in
# raw opcode
831 pc
, msr
, svstate
= cur_state
.pc
, cur_state
.msr
, cur_state
.svstate
833 # also note instruction fetch failed
834 if hasattr(core
, "icache"):
835 fetch_failed
= core
.icache
.i_out
.fetch_failed
838 fetch_failed
= Const(0, 1)
841 # set priv / virt mode on I-Cache, sigh
842 if isinstance(self
.imem
, ICache
):
843 comb
+= self
.imem
.i_in
.priv_mode
.eq(~msr
[MSR
.PR
])
844 comb
+= self
.imem
.i_in
.virt_mode
.eq(msr
[MSR
.IR
]) # Instr. Redir (VM)
846 with m
.FSM(name
='fetch_fsm'):
848 # allow fetch to not run at startup due to I-Cache reset not
849 # having time to settle. power-on-reset holds dbg.core_stopped_i
850 with m
.State("PRE_IDLE"):
851 with m
.If(~dbg
.core_stopped_i
& ~dbg
.core_stop_o
& ~core_rst
):
855 with m
.State("IDLE"):
856 # fetch allowed if not failed and stopped but not stepping
857 # (see dmi.py for how core_stop_o is generated)
858 with m
.If(~fetch_failed
& ~dbg
.core_stop_o
):
859 comb
+= fetch_pc_o_ready
.eq(1)
860 with m
.If(fetch_pc_i_valid
& ~pdecode2
.instr_fault
862 # instruction allowed to go: start by reading the PC
863 # capture the PC and also drop it into Insn Memory
864 # we have joined a pair of combinatorial memory
865 # lookups together. this is Generally Bad.
866 comb
+= self
.imem
.a_pc_i
.eq(pc
)
867 comb
+= self
.imem
.a_i_valid
.eq(1)
868 comb
+= self
.imem
.f_i_valid
.eq(1)
869 m
.next
= "INSN_READ" # move to "wait for bus" phase
871 # dummy pause to find out why simulation is not keeping up
872 with m
.State("INSN_READ"):
873 # when using "single-step" mode, checking dbg.stopping_o
874 # prevents progress. allow fetch to proceed once started
876 #if self.allow_overlap:
877 # stopping = dbg.stopping_o
879 # stopping: jump back to idle
882 with m
.If(self
.imem
.f_busy_o
&
883 ~pdecode2
.instr_fault
): # zzz...
884 # busy but not fetch failed: stay in wait-read
885 comb
+= self
.imem
.a_pc_i
.eq(pc
)
886 comb
+= self
.imem
.a_i_valid
.eq(1)
887 comb
+= self
.imem
.f_i_valid
.eq(1)
889 # not busy (or fetch failed!): instruction fetched
890 # when fetch failed, the instruction gets ignored
892 if hasattr(core
, "icache"):
893 # blech, icache returns actual instruction
894 insn
= self
.imem
.f_instr_o
896 # but these return raw memory
897 insn
= get_insn(self
.imem
.f_instr_o
, cur_state
.pc
)
900 # decode the SVP64 prefix, if any
901 comb
+= svp64
.raw_opcode_in
.eq(insn
)
902 comb
+= svp64
.bigendian
.eq(self
.core_bigendian_i
)
903 # pass the decoded prefix (if any) to PowerDecoder2
904 sync
+= pdecode2
.sv_rm
.eq(svp64
.svp64_rm
)
905 sync
+= pdecode2
.is_svp64_mode
.eq(is_svp64_mode
)
906 # remember whether this is a prefixed instruction,
907 # so the FSM can readily loop when VL==0
908 sync
+= is_svp64_mode
.eq(svp64
.is_svp64_mode
)
909 # calculate the address of the following instruction
910 insn_size
= Mux(svp64
.is_svp64_mode
, 8, 4)
911 sync
+= nia
.eq(cur_state
.pc
+ insn_size
)
912 with m
.If(~svp64
.is_svp64_mode
):
913 # with no prefix, store the instruction
914 # and hand it directly to the next FSM
915 sync
+= dec_opcode_i
.eq(insn
)
916 m
.next
= "INSN_READY"
918 # fetch the rest of the instruction from memory
919 comb
+= self
.imem
.a_pc_i
.eq(cur_state
.pc
+ 4)
920 comb
+= self
.imem
.a_i_valid
.eq(1)
921 comb
+= self
.imem
.f_i_valid
.eq(1)
922 m
.next
= "INSN_READ2"
924 # not SVP64 - 32-bit only
925 sync
+= nia
.eq(cur_state
.pc
+ 4)
926 sync
+= dec_opcode_i
.eq(insn
)
927 if self
.microwatt_compat
:
928 # for verilator debug purposes
929 comb
+= self
.insn
.eq(insn
)
930 comb
+= self
.nia
.eq(cur_state
.pc
)
931 comb
+= self
.msr_o
.eq(cur_state
.msr
)
932 comb
+= self
.nia_req
.eq(1)
933 m
.next
= "INSN_READY"
935 with m
.State("INSN_READ2"):
936 with m
.If(self
.imem
.f_busy_o
): # zzz...
937 # busy: stay in wait-read
938 comb
+= self
.imem
.a_i_valid
.eq(1)
939 comb
+= self
.imem
.f_i_valid
.eq(1)
941 # not busy: instruction fetched
942 if hasattr(core
, "icache"):
943 # blech, icache returns actual instruction
944 insn
= self
.imem
.f_instr_o
946 insn
= get_insn(self
.imem
.f_instr_o
, cur_state
.pc
+4)
947 sync
+= dec_opcode_i
.eq(insn
)
948 m
.next
= "INSN_READY"
949 # TODO: probably can start looking at pdecode2.rm_dec
950 # here or maybe even in INSN_READ state, if svp64_mode
951 # detected, in order to trigger - and wait for - the
954 pmode
= pdecode2
.rm_dec
.predmode
956 if pmode != SVP64PredMode.ALWAYS.value:
957 fire predicate loading FSM and wait before
960 sync += self.srcmask.eq(-1) # set to all 1s
961 sync += self.dstmask.eq(-1) # set to all 1s
962 m.next = "INSN_READY"
965 with m
.State("INSN_READY"):
966 # hand over the instruction, to be decoded
967 comb
+= fetch_insn_o_valid
.eq(1)
968 with m
.If(fetch_insn_i_ready
):
972 def fetch_predicate_fsm(self
, m
,
973 pred_insn_i_valid
, pred_insn_o_ready
,
974 pred_mask_o_valid
, pred_mask_i_ready
):
975 """fetch_predicate_fsm - obtains (constructs in the case of CR)
976 src/dest predicate masks
978 https://bugs.libre-soc.org/show_bug.cgi?id=617
979 the predicates can be read here, by using IntRegs r_ports['pred']
980 or CRRegs r_ports['pred']. in the case of CRs it will have to
981 be done through multiple reads, extracting one relevant at a time.
982 later, a faster way would be to use the 32-bit-wide CR port but
983 this is more complex decoding, here. equivalent code used in
984 ISACaller is "from openpower.decoder.isa.caller import get_predcr"
986 note: this ENTIRE FSM is not to be called when svp64 is disabled
990 pdecode2
= self
.pdecode2
991 rm_dec
= pdecode2
.rm_dec
# SVP64RMModeDecode
992 predmode
= rm_dec
.predmode
993 srcpred
, dstpred
= rm_dec
.srcpred
, rm_dec
.dstpred
994 cr_pred
, int_pred
= self
.cr_pred
, self
.int_pred
# read regfiles
995 # get src/dst step, so we can skip already used mask bits
996 cur_state
= self
.cur_state
997 srcstep
= cur_state
.svstate
.srcstep
998 dststep
= cur_state
.svstate
.dststep
999 cur_vl
= cur_state
.svstate
.vl
1002 sregread
, sinvert
, sunary
, sall1s
= get_predint(m
, srcpred
, 's')
1003 dregread
, dinvert
, dunary
, dall1s
= get_predint(m
, dstpred
, 'd')
1004 sidx
, scrinvert
= get_predcr(m
, srcpred
, 's')
1005 didx
, dcrinvert
= get_predcr(m
, dstpred
, 'd')
1007 # store fetched masks, for either intpred or crpred
1008 # when src/dst step is not zero, the skipped mask bits need to be
1009 # shifted-out, before actually storing them in src/dest mask
1010 new_srcmask
= Signal(64, reset_less
=True)
1011 new_dstmask
= Signal(64, reset_less
=True)
1013 with m
.FSM(name
="fetch_predicate"):
1015 with m
.State("FETCH_PRED_IDLE"):
1016 comb
+= pred_insn_o_ready
.eq(1)
1017 with m
.If(pred_insn_i_valid
):
1018 with m
.If(predmode
== SVP64PredMode
.INT
):
1019 # skip fetching destination mask register, when zero
1021 sync
+= new_dstmask
.eq(-1)
1022 # directly go to fetch source mask register
1023 # guaranteed not to be zero (otherwise predmode
1024 # would be SVP64PredMode.ALWAYS, not INT)
1025 comb
+= int_pred
.addr
.eq(sregread
)
1026 comb
+= int_pred
.ren
.eq(1)
1027 m
.next
= "INT_SRC_READ"
1028 # fetch destination predicate register
1030 comb
+= int_pred
.addr
.eq(dregread
)
1031 comb
+= int_pred
.ren
.eq(1)
1032 m
.next
= "INT_DST_READ"
1033 with m
.Elif(predmode
== SVP64PredMode
.CR
):
1034 # go fetch masks from the CR register file
1035 sync
+= new_srcmask
.eq(0)
1036 sync
+= new_dstmask
.eq(0)
1039 sync
+= self
.srcmask
.eq(-1)
1040 sync
+= self
.dstmask
.eq(-1)
1041 m
.next
= "FETCH_PRED_DONE"
1043 with m
.State("INT_DST_READ"):
1044 # store destination mask
1045 inv
= Repl(dinvert
, 64)
1047 # set selected mask bit for 1<<r3 mode
1048 dst_shift
= Signal(range(64))
1049 comb
+= dst_shift
.eq(self
.int_pred
.o_data
& 0b111111)
1050 sync
+= new_dstmask
.eq(1 << dst_shift
)
1052 # invert mask if requested
1053 sync
+= new_dstmask
.eq(self
.int_pred
.o_data ^ inv
)
1054 # skip fetching source mask register, when zero
1056 sync
+= new_srcmask
.eq(-1)
1057 m
.next
= "FETCH_PRED_SHIFT_MASK"
1058 # fetch source predicate register
1060 comb
+= int_pred
.addr
.eq(sregread
)
1061 comb
+= int_pred
.ren
.eq(1)
1062 m
.next
= "INT_SRC_READ"
1064 with m
.State("INT_SRC_READ"):
1066 inv
= Repl(sinvert
, 64)
1068 # set selected mask bit for 1<<r3 mode
1069 src_shift
= Signal(range(64))
1070 comb
+= src_shift
.eq(self
.int_pred
.o_data
& 0b111111)
1071 sync
+= new_srcmask
.eq(1 << src_shift
)
1073 # invert mask if requested
1074 sync
+= new_srcmask
.eq(self
.int_pred
.o_data ^ inv
)
1075 m
.next
= "FETCH_PRED_SHIFT_MASK"
1077 # fetch masks from the CR register file
1078 # implements the following loop:
1079 # idx, inv = get_predcr(mask)
1081 # for cr_idx in range(vl):
1082 # cr = crl[cr_idx + SVP64CROffs.CRPred] # takes one cycle
1084 # mask |= 1 << cr_idx
1086 with m
.State("CR_READ"):
1087 # CR index to be read, which will be ready by the next cycle
1088 cr_idx
= Signal
.like(cur_vl
, reset_less
=True)
1089 # submit the read operation to the regfile
1090 with m
.If(cr_idx
!= cur_vl
):
1091 # the CR read port is unary ...
1093 # ... in MSB0 convention ...
1094 # ren = 1 << (7 - cr_idx)
1095 # ... and with an offset:
1096 # ren = 1 << (7 - off - cr_idx)
1097 idx
= SVP64CROffs
.CRPred
+ cr_idx
1098 comb
+= cr_pred
.ren
.eq(1 << (7 - idx
))
1099 # signal data valid in the next cycle
1100 cr_read
= Signal(reset_less
=True)
1101 sync
+= cr_read
.eq(1)
1102 # load the next index
1103 sync
+= cr_idx
.eq(cr_idx
+ 1)
1106 sync
+= cr_read
.eq(0)
1107 sync
+= cr_idx
.eq(0)
1108 m
.next
= "FETCH_PRED_SHIFT_MASK"
1110 # compensate for the one cycle delay on the regfile
1111 cur_cr_idx
= Signal
.like(cur_vl
)
1112 comb
+= cur_cr_idx
.eq(cr_idx
- 1)
1113 # read the CR field, select the appropriate bit
1114 cr_field
= Signal(4)
1117 comb
+= cr_field
.eq(cr_pred
.o_data
)
1118 comb
+= scr_bit
.eq(cr_field
.bit_select(sidx
, 1)
1120 comb
+= dcr_bit
.eq(cr_field
.bit_select(didx
, 1)
1122 # set the corresponding mask bit
1123 bit_to_set
= Signal
.like(self
.srcmask
)
1124 comb
+= bit_to_set
.eq(1 << cur_cr_idx
)
1126 sync
+= new_srcmask
.eq(new_srcmask | bit_to_set
)
1128 sync
+= new_dstmask
.eq(new_dstmask | bit_to_set
)
1130 with m
.State("FETCH_PRED_SHIFT_MASK"):
1131 # shift-out skipped mask bits
1132 sync
+= self
.srcmask
.eq(new_srcmask
>> srcstep
)
1133 sync
+= self
.dstmask
.eq(new_dstmask
>> dststep
)
1134 m
.next
= "FETCH_PRED_DONE"
1136 with m
.State("FETCH_PRED_DONE"):
1137 comb
+= pred_mask_o_valid
.eq(1)
1138 with m
.If(pred_mask_i_ready
):
1139 m
.next
= "FETCH_PRED_IDLE"
1141 def issue_fsm(self
, m
, core
, nia
,
1142 dbg
, core_rst
, is_svp64_mode
,
1143 fetch_pc_o_ready
, fetch_pc_i_valid
,
1144 fetch_insn_o_valid
, fetch_insn_i_ready
,
1145 pred_insn_i_valid
, pred_insn_o_ready
,
1146 pred_mask_o_valid
, pred_mask_i_ready
,
1147 exec_insn_i_valid
, exec_insn_o_ready
,
1148 exec_pc_o_valid
, exec_pc_i_ready
):
1151 decode / issue FSM. this interacts with the "fetch" FSM
1152 through fetch_insn_ready/valid (incoming) and fetch_pc_ready/valid
1153 (outgoing). also interacts with the "execute" FSM
1154 through exec_insn_ready/valid (outgoing) and exec_pc_ready/valid
1156 SVP64 RM prefixes have already been set up by the
1157 "fetch" phase, so execute is fairly straightforward.
1162 pdecode2
= self
.pdecode2
1163 cur_state
= self
.cur_state
1164 new_svstate
= self
.new_svstate
1167 dec_opcode_i
= pdecode2
.dec
.raw_opcode_in
# raw opcode
1169 # for updating svstate (things like srcstep etc.)
1170 comb
+= new_svstate
.eq(cur_state
.svstate
)
1172 # precalculate srcstep+1 and dststep+1
1173 cur_srcstep
= cur_state
.svstate
.srcstep
1174 cur_dststep
= cur_state
.svstate
.dststep
1175 next_srcstep
= Signal
.like(cur_srcstep
)
1176 next_dststep
= Signal
.like(cur_dststep
)
1177 comb
+= next_srcstep
.eq(cur_state
.svstate
.srcstep
+1)
1178 comb
+= next_dststep
.eq(cur_state
.svstate
.dststep
+1)
1180 # note if an exception happened. in a pipelined or OoO design
1181 # this needs to be accompanied by "shadowing" (or stalling)
1182 exc_happened
= self
.core
.o
.exc_happened
1183 # also note instruction fetch failed
1184 if hasattr(core
, "icache"):
1185 fetch_failed
= core
.icache
.i_out
.fetch_failed
1187 # set to fault in decoder
1188 # update (highest priority) instruction fault
1189 rising_fetch_failed
= rising_edge(m
, fetch_failed
)
1190 with m
.If(rising_fetch_failed
):
1191 sync
+= pdecode2
.instr_fault
.eq(1)
1193 fetch_failed
= Const(0, 1)
1194 flush_needed
= False
1196 sync
+= fetch_pc_i_valid
.eq(0)
1198 with m
.FSM(name
="issue_fsm"):
1200 with m
.State("PRE_IDLE"):
1201 with m
.If(~dbg
.core_stop_o
& ~core_rst
):
1202 m
.next
= "ISSUE_START"
1204 # sync with the "fetch" phase which is reading the instruction
1205 # at this point, there is no instruction running, that
1206 # could inadvertently update the PC.
1207 with m
.State("ISSUE_START"):
1208 # reset instruction fault
1209 sync
+= pdecode2
.instr_fault
.eq(0)
1210 # wait on "core stop" release, before next fetch
1211 # need to do this here, in case we are in a VL==0 loop
1212 with m
.If(~dbg
.core_stop_o
& ~core_rst
):
1213 sync
+= fetch_pc_i_valid
.eq(1) # tell fetch to start
1214 sync
+= cur_state
.pc
.eq(dbg
.state
.pc
)
1215 sync
+= cur_state
.svstate
.eq(dbg
.state
.svstate
)
1216 sync
+= cur_state
.msr
.eq(dbg
.state
.msr
)
1217 with m
.If(fetch_pc_o_ready
): # fetch acknowledged us
1218 m
.next
= "INSN_WAIT"
1220 # tell core it's stopped, and acknowledge debug handshake
1221 comb
+= dbg
.core_stopped_i
.eq(1)
1222 # while stopped, allow updating SVSTATE
1223 with m
.If(self
.svstate_i
.ok
):
1224 comb
+= new_svstate
.eq(self
.svstate_i
.data
)
1225 comb
+= self
.update_svstate
.eq(1)
1226 sync
+= self
.sv_changed
.eq(1)
1228 # wait for an instruction to arrive from Fetch
1229 with m
.State("INSN_WAIT"):
1230 # when using "single-step" mode, checking dbg.stopping_o
1231 # prevents progress. allow issue to proceed once started
1233 #if self.allow_overlap:
1234 # stopping = dbg.stopping_o
1235 with m
.If(stopping
):
1236 # stopping: jump back to idle
1237 m
.next
= "ISSUE_START"
1239 # request the icache to stop asserting "failed"
1240 comb
+= core
.icache
.flush_in
.eq(1)
1241 # stop instruction fault
1242 sync
+= pdecode2
.instr_fault
.eq(0)
1244 comb
+= fetch_insn_i_ready
.eq(1)
1245 with m
.If(fetch_insn_o_valid
):
1246 # loop into ISSUE_START if it's a SVP64 instruction
1247 # and VL == 0. this because VL==0 is a for-loop
1248 # from 0 to 0 i.e. always, always a NOP.
1249 cur_vl
= cur_state
.svstate
.vl
1250 with m
.If(is_svp64_mode
& (cur_vl
== 0)):
1251 # update the PC before fetching the next instruction
1252 # since we are in a VL==0 loop, no instruction was
1253 # executed that we could be overwriting
1254 comb
+= self
.state_w_pc
.wen
.eq(1 << StateRegs
.PC
)
1255 comb
+= self
.state_w_pc
.i_data
.eq(nia
)
1256 comb
+= self
.insn_done
.eq(1)
1257 m
.next
= "ISSUE_START"
1260 m
.next
= "PRED_START" # fetching predicate
1262 m
.next
= "DECODE_SV" # skip predication
1264 with m
.State("PRED_START"):
1265 comb
+= pred_insn_i_valid
.eq(1) # tell fetch_pred to start
1266 with m
.If(pred_insn_o_ready
): # fetch_pred acknowledged us
1267 m
.next
= "MASK_WAIT"
1269 with m
.State("MASK_WAIT"):
1270 comb
+= pred_mask_i_ready
.eq(1) # ready to receive the masks
1271 with m
.If(pred_mask_o_valid
): # predication masks are ready
1272 m
.next
= "PRED_SKIP"
1274 # skip zeros in predicate
1275 with m
.State("PRED_SKIP"):
1276 with m
.If(~is_svp64_mode
):
1277 m
.next
= "DECODE_SV" # nothing to do
1280 pred_src_zero
= pdecode2
.rm_dec
.pred_sz
1281 pred_dst_zero
= pdecode2
.rm_dec
.pred_dz
1283 # new srcstep, after skipping zeros
1284 skip_srcstep
= Signal
.like(cur_srcstep
)
1285 # value to be added to the current srcstep
1286 src_delta
= Signal
.like(cur_srcstep
)
1287 # add leading zeros to srcstep, if not in zero mode
1288 with m
.If(~pred_src_zero
):
1289 # priority encoder (count leading zeros)
1290 # append guard bit, in case the mask is all zeros
1291 pri_enc_src
= PriorityEncoder(65)
1292 m
.submodules
.pri_enc_src
= pri_enc_src
1293 comb
+= pri_enc_src
.i
.eq(Cat(self
.srcmask
,
1295 comb
+= src_delta
.eq(pri_enc_src
.o
)
1296 # apply delta to srcstep
1297 comb
+= skip_srcstep
.eq(cur_srcstep
+ src_delta
)
1298 # shift-out all leading zeros from the mask
1299 # plus the leading "one" bit
1300 # TODO count leading zeros and shift-out the zero
1301 # bits, in the same step, in hardware
1302 sync
+= self
.srcmask
.eq(self
.srcmask
>> (src_delta
+1))
1304 # same as above, but for dststep
1305 skip_dststep
= Signal
.like(cur_dststep
)
1306 dst_delta
= Signal
.like(cur_dststep
)
1307 with m
.If(~pred_dst_zero
):
1308 pri_enc_dst
= PriorityEncoder(65)
1309 m
.submodules
.pri_enc_dst
= pri_enc_dst
1310 comb
+= pri_enc_dst
.i
.eq(Cat(self
.dstmask
,
1312 comb
+= dst_delta
.eq(pri_enc_dst
.o
)
1313 comb
+= skip_dststep
.eq(cur_dststep
+ dst_delta
)
1314 sync
+= self
.dstmask
.eq(self
.dstmask
>> (dst_delta
+1))
1316 # TODO: initialize mask[VL]=1 to avoid passing past VL
1317 with m
.If((skip_srcstep
>= cur_vl
) |
1318 (skip_dststep
>= cur_vl
)):
1319 # end of VL loop. Update PC and reset src/dst step
1320 comb
+= self
.state_w_pc
.wen
.eq(1 << StateRegs
.PC
)
1321 comb
+= self
.state_w_pc
.i_data
.eq(nia
)
1322 comb
+= new_svstate
.srcstep
.eq(0)
1323 comb
+= new_svstate
.dststep
.eq(0)
1324 comb
+= self
.update_svstate
.eq(1)
1325 # synchronize with the simulator
1326 comb
+= self
.insn_done
.eq(1)
1328 m
.next
= "ISSUE_START"
1330 # update new src/dst step
1331 comb
+= new_svstate
.srcstep
.eq(skip_srcstep
)
1332 comb
+= new_svstate
.dststep
.eq(skip_dststep
)
1333 comb
+= self
.update_svstate
.eq(1)
1335 m
.next
= "DECODE_SV"
1337 # pass predicate mask bits through to satellite decoders
1338 # TODO: for SIMD this will be *multiple* bits
1339 sync
+= core
.i
.sv_pred_sm
.eq(self
.srcmask
[0])
1340 sync
+= core
.i
.sv_pred_dm
.eq(self
.dstmask
[0])
1342 # after src/dst step have been updated, we are ready
1343 # to decode the instruction
1344 with m
.State("DECODE_SV"):
1345 # decode the instruction
1346 with m
.If(~fetch_failed
):
1347 sync
+= pdecode2
.instr_fault
.eq(0)
1348 sync
+= core
.i
.e
.eq(pdecode2
.e
)
1349 sync
+= core
.i
.state
.eq(cur_state
)
1350 sync
+= core
.i
.raw_insn_i
.eq(dec_opcode_i
)
1351 sync
+= core
.i
.bigendian_i
.eq(self
.core_bigendian_i
)
1353 sync
+= core
.i
.sv_rm
.eq(pdecode2
.sv_rm
)
1354 # set RA_OR_ZERO detection in satellite decoders
1355 sync
+= core
.i
.sv_a_nz
.eq(pdecode2
.sv_a_nz
)
1356 # and svp64 detection
1357 sync
+= core
.i
.is_svp64_mode
.eq(is_svp64_mode
)
1358 # and svp64 bit-rev'd ldst mode
1359 ldst_dec
= pdecode2
.use_svp64_ldst_dec
1360 sync
+= core
.i
.use_svp64_ldst_dec
.eq(ldst_dec
)
1361 # after decoding, reset any previous exception condition,
1362 # allowing it to be set again during the next execution
1363 sync
+= pdecode2
.ldst_exc
.eq(0)
1365 m
.next
= "INSN_EXECUTE" # move to "execute"
1367 # handshake with execution FSM, move to "wait" once acknowledged
1368 with m
.State("INSN_EXECUTE"):
1369 # when using "single-step" mode, checking dbg.stopping_o
1370 # prevents progress. allow execute to proceed once started
1372 #if self.allow_overlap:
1373 # stopping = dbg.stopping_o
1374 with m
.If(stopping
):
1375 # stopping: jump back to idle
1376 m
.next
= "ISSUE_START"
1378 # request the icache to stop asserting "failed"
1379 comb
+= core
.icache
.flush_in
.eq(1)
1380 # stop instruction fault
1381 sync
+= pdecode2
.instr_fault
.eq(0)
1383 comb
+= exec_insn_i_valid
.eq(1) # trigger execute
1384 with m
.If(exec_insn_o_ready
): # execute acknowledged us
1385 m
.next
= "EXECUTE_WAIT"
1387 with m
.State("EXECUTE_WAIT"):
1388 comb
+= exec_pc_i_ready
.eq(1)
1389 # see https://bugs.libre-soc.org/show_bug.cgi?id=636
1390 # the exception info needs to be blatted into
1391 # pdecode.ldst_exc, and the instruction "re-run".
1392 # when ldst_exc.happened is set, the PowerDecoder2
1393 # reacts very differently: it re-writes the instruction
1394 # with a "trap" (calls PowerDecoder2.trap()) which
1395 # will *overwrite* whatever was requested and jump the
1396 # PC to the exception address, as well as alter MSR.
1397 # nothing else needs to be done other than to note
1398 # the change of PC and MSR (and, later, SVSTATE)
1399 with m
.If(exc_happened
):
1400 mmu
= core
.fus
.get_exc("mmu0")
1401 ldst
= core
.fus
.get_exc("ldst0")
1403 with m
.If(fetch_failed
):
1404 # instruction fetch: exception is from MMU
1405 # reset instr_fault (highest priority)
1406 sync
+= pdecode2
.ldst_exc
.eq(mmu
)
1407 sync
+= pdecode2
.instr_fault
.eq(0)
1409 # request icache to stop asserting "failed"
1410 comb
+= core
.icache
.flush_in
.eq(1)
1411 with m
.If(~fetch_failed
):
1412 # otherwise assume it was a LDST exception
1413 sync
+= pdecode2
.ldst_exc
.eq(ldst
)
1415 with m
.If(exec_pc_o_valid
):
1417 # was this the last loop iteration?
1419 cur_vl
= cur_state
.svstate
.vl
1420 comb
+= is_last
.eq(next_srcstep
== cur_vl
)
1422 with m
.If(pdecode2
.instr_fault
):
1423 # reset instruction fault, try again
1424 sync
+= pdecode2
.instr_fault
.eq(0)
1425 m
.next
= "ISSUE_START"
1427 # return directly to Decode if Execute generated an
1429 with m
.Elif(pdecode2
.ldst_exc
.happened
):
1430 m
.next
= "DECODE_SV"
1432 # if MSR, PC or SVSTATE were changed by the previous
1433 # instruction, go directly back to Fetch, without
1434 # updating either MSR PC or SVSTATE
1435 with m
.Elif(self
.msr_changed | self
.pc_changed |
1437 m
.next
= "ISSUE_START"
1439 # also return to Fetch, when no output was a vector
1440 # (regardless of SRCSTEP and VL), or when the last
1441 # instruction was really the last one of the VL loop
1442 with m
.Elif((~pdecode2
.loop_continue
) | is_last
):
1443 # before going back to fetch, update the PC state
1444 # register with the NIA.
1445 # ok here we are not reading the branch unit.
1446 # TODO: this just blithely overwrites whatever
1447 # pipeline updated the PC
1448 comb
+= self
.state_w_pc
.wen
.eq(1 << StateRegs
.PC
)
1449 comb
+= self
.state_w_pc
.i_data
.eq(nia
)
1450 # reset SRCSTEP before returning to Fetch
1452 with m
.If(pdecode2
.loop_continue
):
1453 comb
+= new_svstate
.srcstep
.eq(0)
1454 comb
+= new_svstate
.dststep
.eq(0)
1455 comb
+= self
.update_svstate
.eq(1)
1457 comb
+= new_svstate
.srcstep
.eq(0)
1458 comb
+= new_svstate
.dststep
.eq(0)
1459 comb
+= self
.update_svstate
.eq(1)
1460 m
.next
= "ISSUE_START"
1462 # returning to Execute? then, first update SRCSTEP
1464 comb
+= new_svstate
.srcstep
.eq(next_srcstep
)
1465 comb
+= new_svstate
.dststep
.eq(next_dststep
)
1466 comb
+= self
.update_svstate
.eq(1)
1467 # return to mask skip loop
1468 m
.next
= "PRED_SKIP"
1471 # check if svstate needs updating: if so, write it to State Regfile
1472 with m
.If(self
.update_svstate
):
1473 sync
+= cur_state
.svstate
.eq(self
.new_svstate
) # for next clock
1475 def execute_fsm(self
, m
, core
,
1476 exec_insn_i_valid
, exec_insn_o_ready
,
1477 exec_pc_o_valid
, exec_pc_i_ready
):
1480 execute FSM. this interacts with the "issue" FSM
1481 through exec_insn_ready/valid (incoming) and exec_pc_ready/valid
1482 (outgoing). SVP64 RM prefixes have already been set up by the
1483 "issue" phase, so execute is fairly straightforward.
1489 pdecode2
= self
.pdecode2
1492 core_busy_o
= core
.n
.o_data
.busy_o
# core is busy
1493 core_ivalid_i
= core
.p
.i_valid
# instruction is valid
1495 if hasattr(core
, "icache"):
1496 fetch_failed
= core
.icache
.i_out
.fetch_failed
1498 fetch_failed
= Const(0, 1)
1500 with m
.FSM(name
="exec_fsm"):
1502 # waiting for instruction bus (stays there until not busy)
1503 with m
.State("INSN_START"):
1504 comb
+= exec_insn_o_ready
.eq(1)
1505 with m
.If(exec_insn_i_valid
):
1506 comb
+= core_ivalid_i
.eq(1) # instruction is valid/issued
1507 sync
+= self
.sv_changed
.eq(0)
1508 sync
+= self
.pc_changed
.eq(0)
1509 sync
+= self
.msr_changed
.eq(0)
1510 with m
.If(core
.p
.o_ready
): # only move if accepted
1511 m
.next
= "INSN_ACTIVE" # move to "wait completion"
1513 # instruction started: must wait till it finishes
1514 with m
.State("INSN_ACTIVE"):
1515 # note changes to MSR, PC and SVSTATE, and DEC/TB
1516 # these last two are done together, and passed to the
1518 with m
.If(self
.state_nia
.wen
& (1 << StateRegs
.SVSTATE
)):
1519 sync
+= self
.sv_changed
.eq(1)
1520 with m
.If(self
.state_nia
.wen
& (1 << StateRegs
.MSR
)):
1521 sync
+= self
.msr_changed
.eq(1)
1522 with m
.If(self
.state_nia
.wen
& (1 << StateRegs
.PC
)):
1523 sync
+= self
.pc_changed
.eq(1)
1524 with m
.If((self
.state_spr
.wen
&
1525 ((1 << StateRegs
.DEC
) |
(1 << StateRegs
.TB
))).bool()):
1526 comb
+= self
.pause_dec_tb
.eq(1)
1527 with m
.If(~core_busy_o
): # instruction done!
1528 comb
+= exec_pc_o_valid
.eq(1)
1529 with m
.If(exec_pc_i_ready
):
1530 # when finished, indicate "done".
1531 # however, if there was an exception, the instruction
1532 # is *not* yet done. this is an implementation
1533 # detail: we choose to implement exceptions by
1534 # taking the exception information from the LDST
1535 # unit, putting that *back* into the PowerDecoder2,
1536 # and *re-running the entire instruction*.
1537 # if we erroneously indicate "done" here, it is as if
1538 # there were *TWO* instructions:
1539 # 1) the failed LDST 2) a TRAP.
1540 with m
.If(~pdecode2
.ldst_exc
.happened
&
1541 ~pdecode2
.instr_fault
):
1542 comb
+= self
.insn_done
.eq(1)
1543 m
.next
= "INSN_START" # back to fetch
1544 # terminate returns directly to INSN_START
1545 with m
.If(dbg
.terminate_i
):
1546 # comb += self.insn_done.eq(1) - no because it's not
1547 m
.next
= "INSN_START" # back to fetch
1549 def elaborate(self
, platform
):
1550 m
= super().elaborate(platform
)
1552 comb
, sync
= m
.d
.comb
, m
.d
.sync
1553 cur_state
= self
.cur_state
1554 pdecode2
= self
.pdecode2
1558 # set up peripherals and core
1559 core_rst
= self
.core_rst
1561 # indicate to outside world if any FU is still executing
1562 comb
+= self
.any_busy
.eq(core
.n
.o_data
.any_busy_o
) # any FU executing
1564 # address of the next instruction, in the absence of a branch
1565 # depends on the instruction size
1568 # connect up debug signals
1569 with m
.If(core
.o
.core_terminate_o
):
1570 comb
+= dbg
.terminate_i
.eq(1)
1572 # pass the prefix mode from Fetch to Issue, so the latter can loop
1574 is_svp64_mode
= Signal()
1576 # there are *THREE^WFOUR-if-SVP64-enabled* FSMs, fetch (32/64-bit)
1577 # issue, decode/execute, now joined by "Predicate fetch/calculate".
1578 # these are the handshake signals between each
1580 # fetch FSM can run as soon as the PC is valid
1581 fetch_pc_i_valid
= Signal() # Execute tells Fetch "start next read"
1582 fetch_pc_o_ready
= Signal() # Fetch Tells SVSTATE "proceed"
1584 # fetch FSM hands over the instruction to be decoded / issued
1585 fetch_insn_o_valid
= Signal()
1586 fetch_insn_i_ready
= Signal()
1588 # predicate fetch FSM decodes and fetches the predicate
1589 pred_insn_i_valid
= Signal()
1590 pred_insn_o_ready
= Signal()
1592 # predicate fetch FSM delivers the masks
1593 pred_mask_o_valid
= Signal()
1594 pred_mask_i_ready
= Signal()
1596 # issue FSM delivers the instruction to the be executed
1597 exec_insn_i_valid
= Signal()
1598 exec_insn_o_ready
= Signal()
1600 # execute FSM, hands over the PC/SVSTATE back to the issue FSM
1601 exec_pc_o_valid
= Signal()
1602 exec_pc_i_ready
= Signal()
1604 # the FSMs here are perhaps unusual in that they detect conditions
1605 # then "hold" information, combinatorially, for the core
1606 # (as opposed to using sync - which would be on a clock's delay)
1607 # this includes the actual opcode, valid flags and so on.
1609 # Fetch, then predicate fetch, then Issue, then Execute.
1610 # Issue is where the VL for-loop # lives. the ready/valid
1611 # signalling is used to communicate between the four.
1613 self
.fetch_fsm(m
, dbg
, core
, core_rst
, nia
, is_svp64_mode
,
1614 fetch_pc_o_ready
, fetch_pc_i_valid
,
1615 fetch_insn_o_valid
, fetch_insn_i_ready
)
1617 self
.issue_fsm(m
, core
, nia
,
1618 dbg
, core_rst
, is_svp64_mode
,
1619 fetch_pc_o_ready
, fetch_pc_i_valid
,
1620 fetch_insn_o_valid
, fetch_insn_i_ready
,
1621 pred_insn_i_valid
, pred_insn_o_ready
,
1622 pred_mask_o_valid
, pred_mask_i_ready
,
1623 exec_insn_i_valid
, exec_insn_o_ready
,
1624 exec_pc_o_valid
, exec_pc_i_ready
)
1627 self
.fetch_predicate_fsm(m
,
1628 pred_insn_i_valid
, pred_insn_o_ready
,
1629 pred_mask_o_valid
, pred_mask_i_ready
)
1631 self
.execute_fsm(m
, core
,
1632 exec_insn_i_valid
, exec_insn_o_ready
,
1633 exec_pc_o_valid
, exec_pc_i_ready
)
1635 # whatever was done above, over-ride it if core reset is held.
1636 # set NIA to pc_at_reset
1637 with m
.If(core_rst
):
1638 sync
+= nia
.eq(self
.core
.pc_at_reset
)
1643 class TestIssuer(Elaboratable
):
1644 def __init__(self
, pspec
):
1645 self
.ti
= TestIssuerInternal(pspec
)
1646 self
.pll
= DummyPLL(instance
=True)
1648 self
.dbg_rst_i
= Signal(reset_less
=True)
1650 # PLL direct clock or not
1651 self
.pll_en
= hasattr(pspec
, "use_pll") and pspec
.use_pll
1653 self
.pll_test_o
= Signal(reset_less
=True)
1654 self
.pll_vco_o
= Signal(reset_less
=True)
1655 self
.clk_sel_i
= Signal(2, reset_less
=True)
1656 self
.ref_clk
= ClockSignal() # can't rename it but that's ok
1657 self
.pllclk_clk
= ClockSignal("pllclk")
1659 def elaborate(self
, platform
):
1663 # TestIssuer nominally runs at main clock, actually it is
1664 # all combinatorial internally except for coresync'd components
1665 m
.submodules
.ti
= ti
= self
.ti
1668 # ClockSelect runs at PLL output internal clock rate
1669 m
.submodules
.wrappll
= pll
= self
.pll
1671 # add clock domains from PLL
1672 cd_pll
= ClockDomain("pllclk")
1675 # PLL clock established. has the side-effect of running clklsel
1676 # at the PLL's speed (see DomainRenamer("pllclk") above)
1677 pllclk
= self
.pllclk_clk
1678 comb
+= pllclk
.eq(pll
.clk_pll_o
)
1680 # wire up external 24mhz to PLL
1681 #comb += pll.clk_24_i.eq(self.ref_clk)
1682 # output 18 mhz PLL test signal, and analog oscillator out
1683 comb
+= self
.pll_test_o
.eq(pll
.pll_test_o
)
1684 comb
+= self
.pll_vco_o
.eq(pll
.pll_vco_o
)
1686 # input to pll clock selection
1687 comb
+= pll
.clk_sel_i
.eq(self
.clk_sel_i
)
1689 # now wire up ResetSignals. don't mind them being in this domain
1690 pll_rst
= ResetSignal("pllclk")
1691 comb
+= pll_rst
.eq(ResetSignal())
1693 # internal clock is set to selector clock-out. has the side-effect of
1694 # running TestIssuer at this speed (see DomainRenamer("intclk") above)
1695 # debug clock runs at coresync internal clock
1696 if self
.ti
.dbg_domain
!= 'sync':
1697 cd_dbgsync
= ClockDomain("dbgsync")
1698 intclk
= ClockSignal(self
.ti
.core_domain
)
1699 dbgclk
= ClockSignal(self
.ti
.dbg_domain
)
1700 # XXX BYPASS PLL XXX
1701 # XXX BYPASS PLL XXX
1702 # XXX BYPASS PLL XXX
1704 comb
+= intclk
.eq(self
.ref_clk
)
1705 assert self
.ti
.core_domain
!= 'sync', \
1706 "cannot set core_domain to sync and use pll at the same time"
1708 if self
.ti
.core_domain
!= 'sync':
1709 comb
+= intclk
.eq(ClockSignal())
1710 if self
.ti
.dbg_domain
!= 'sync':
1711 dbgclk
= ClockSignal(self
.ti
.dbg_domain
)
1712 comb
+= dbgclk
.eq(intclk
)
1713 comb
+= self
.ti
.dbg_rst_i
.eq(self
.dbg_rst_i
)
1718 return list(self
.ti
.ports()) + list(self
.pll
.ports()) + \
1719 [ClockSignal(), ResetSignal()]
1721 def external_ports(self
):
1722 ports
= self
.ti
.external_ports()
1723 ports
.append(ClockSignal())
1724 ports
.append(ResetSignal())
1726 ports
.append(self
.clk_sel_i
)
1727 ports
.append(self
.pll
.clk_24_i
)
1728 ports
.append(self
.pll_test_o
)
1729 ports
.append(self
.pll_vco_o
)
1730 ports
.append(self
.pllclk_clk
)
1731 ports
.append(self
.ref_clk
)
1735 if __name__
== '__main__':
1736 units
= {'alu': 1, 'cr': 1, 'branch': 1, 'trap': 1, 'logical': 1,
1742 pspec
= TestMemPspec(ldst_ifacetype
='bare_wb',
1743 imem_ifacetype
='bare_wb',
1748 dut
= TestIssuer(pspec
)
1749 vl
= main(dut
, ports
=dut
.ports(), name
="test_issuer")
1751 if len(sys
.argv
) == 1:
1752 vl
= rtlil
.convert(dut
, ports
=dut
.external_ports(), name
="test_issuer")
1753 with
open("test_issuer.il", "w") as f
: