59b463b0a453e02391a38e82b629fff6e00e5686
3 not in any way intended for production use. this runs a FSM that:
5 * reads the Program Counter from FastRegs
6 * reads an instruction from a fixed-size Test Memory
7 * issues it to the Simple Core
8 * waits for it to complete
10 * does it all over again
12 the purpose of this module is to verify the functional correctness
13 of the Function Units in the absolute simplest and clearest possible
14 way, and to at provide something that can be further incrementally
18 from nmigen
import Elaboratable
, Module
, Signal
19 from nmigen
.cli
import rtlil
20 from nmigen
.cli
import main
23 from soc
.decoder
.decode2execute1
import Data
24 from soc
.experiment
.testmem
import TestMemory
# test only for instructions
25 from soc
.regfile
.regfiles
import FastRegs
26 from soc
.simple
.core
import NonProductionCore
27 from soc
.config
.test
.test_loadstore
import TestMemPspec
28 from soc
.config
.ifetch
import ConfigFetchUnit
29 from soc
.decoder
.power_enums
import MicrOp
32 class TestIssuer(Elaboratable
):
33 """TestIssuer - reads instructions from TestMemory and issues them
35 efficiency and speed is not the main goal here: functional correctness is.
37 def __init__(self
, pspec
):
38 # main instruction core
39 self
.core
= core
= NonProductionCore(pspec
)
41 # Test Instruction memory
42 self
.imem
= ConfigFetchUnit(pspec
).fu
43 # one-row cache of instruction read
44 self
.iline
= Signal(64) # one instruction line
45 self
.iprev_adr
= Signal(64) # previous address: if different, do read
47 # instruction go/monitor
48 self
.go_insn_i
= Signal()
49 self
.pc_o
= Signal(64, reset_less
=True)
50 self
.pc_i
= Data(64, "pc_i") # set "ok" to indicate "please change me"
51 self
.core_start_i
= Signal()
52 self
.core_stop_i
= Signal()
53 self
.core_bigendian_i
= Signal()
54 self
.busy_o
= Signal(reset_less
=True)
55 self
.halted_o
= Signal(reset_less
=True)
56 self
.memerr_o
= Signal(reset_less
=True)
58 # FAST regfile read /write ports for PC and MSR
59 self
.fast_r_pc
= self
.core
.regs
.rf
['fast'].r_ports
['d_rd1'] # PC rd
60 self
.fast_w_pc
= self
.core
.regs
.rf
['fast'].w_ports
['d_wr1'] # PC wr
61 self
.fast_r_msr
= self
.core
.regs
.rf
['fast'].r_ports
['d_rd2'] # MSR rd
63 # hack method of keeping an eye on whether branch/trap set the PC
64 self
.fast_nia
= self
.core
.regs
.rf
['fast'].w_ports
['nia']
65 self
.fast_nia
.wen
.name
= 'fast_nia_wen'
67 def elaborate(self
, platform
):
69 comb
, sync
= m
.d
.comb
, m
.d
.sync
71 m
.submodules
.core
= core
= self
.core
72 m
.submodules
.imem
= imem
= self
.imem
74 # busy/halted signals from core
75 comb
+= self
.busy_o
.eq(core
.busy_o
)
76 comb
+= self
.halted_o
.eq(core
.core_terminated_o
)
77 comb
+= self
.core_start_i
.eq(core
.core_start_i
)
78 comb
+= self
.core_stop_i
.eq(core
.core_stop_i
)
79 comb
+= self
.core_bigendian_i
.eq(core
.bigendian_i
)
81 # temporary hack: says "go" immediately for both address gen and ST
83 ldst
= core
.fus
.fus
['ldst0']
84 m
.d
.comb
+= ldst
.ad
.go
.eq(ldst
.ad
.rel
) # link addr-go direct to rel
85 m
.d
.comb
+= ldst
.st
.go
.eq(ldst
.st
.rel
) # link store-go direct to rel
87 # PC and instruction from I-Memory
88 current_insn
= Signal(32) # current fetched instruction (note sync)
89 cur_pc
= Signal(64) # current PC (note it is reset/sync)
90 pc_changed
= Signal() # note write to PC
91 comb
+= self
.pc_o
.eq(cur_pc
)
94 # MSR (temp and latched)
95 cur_msr
= Signal(64) # current MSR (note it is reset/sync)
96 msr
= Signal(64, reset_less
=True)
98 # next instruction (+4 on current)
99 nia
= Signal(64, reset_less
=True)
100 comb
+= nia
.eq(cur_pc
+ 4)
103 core_busy_o
= core
.busy_o
# core is busy
104 core_ivalid_i
= core
.ivalid_i
# instruction is valid
105 core_issue_i
= core
.issue_i
# instruction is issued
106 core_be_i
= core
.bigendian_i
# bigendian mode
107 core_opcode_i
= core
.raw_opcode_i
# raw opcode
109 insn_type
= core
.pdecode2
.e
.do
.insn_type
110 insn_msr
= core
.pdecode2
.msr
112 # only run if not in halted state
113 with m
.If(~core
.core_terminated_o
):
115 # actually use a nmigen FSM for the first time (w00t)
116 # this FSM is perhaps unusual in that it detects conditions
117 # then "holds" information, combinatorially, for the core
118 # (as opposed to using sync - which would be on a clock's delay)
119 # this includes the actual opcode, valid flags and so on.
123 with m
.State("IDLE"):
124 sync
+= pc_changed
.eq(0)
125 with m
.If(self
.go_insn_i
):
126 # instruction allowed to go: start by reading the PC
127 pc
= Signal(64, reset_less
=True)
128 with m
.If(self
.pc_i
.ok
):
129 # incoming override (start from pc_i)
130 comb
+= pc
.eq(self
.pc_i
.data
)
132 # otherwise read FastRegs regfile for PC
133 comb
+= self
.fast_r_pc
.ren
.eq(1<<FastRegs
.PC
)
134 comb
+= pc
.eq(self
.fast_r_pc
.data_o
)
135 # capture the PC and also drop it into Insn Memory
136 # we have joined a pair of combinatorial memory
137 # lookups together. this is Generally Bad.
138 comb
+= self
.imem
.a_pc_i
.eq(pc
)
139 comb
+= self
.imem
.a_valid_i
.eq(1)
140 comb
+= self
.imem
.f_valid_i
.eq(1)
141 sync
+= cur_pc
.eq(pc
)
142 m
.next
= "INSN_READ" # move to "wait for bus" phase
144 # waiting for instruction bus (stays there until not busy)
145 with m
.State("INSN_READ"):
146 with m
.If(self
.imem
.f_busy_o
): # zzz...
147 # busy: stay in wait-read
148 comb
+= self
.imem
.a_valid_i
.eq(1)
149 comb
+= self
.imem
.f_valid_i
.eq(1)
151 # not busy: instruction fetched
152 insn
= self
.imem
.f_instr_o
.word_select(cur_pc
[2], 32)
153 comb
+= current_insn
.eq(insn
)
154 comb
+= core_ivalid_i
.eq(1) # instruction is valid
155 comb
+= core_issue_i
.eq(1) # and issued
156 comb
+= core_opcode_i
.eq(current_insn
) # actual opcode
157 sync
+= ilatch
.eq(current_insn
) # latch current insn
160 comb
+= self
.fast_r_msr
.ren
.eq(1<<FastRegs
.MSR
)
161 comb
+= msr
.eq(self
.fast_r_msr
.data_o
)
162 comb
+= insn_msr
.eq(msr
)
163 sync
+= cur_msr
.eq(msr
) # latch current MSR
165 m
.next
= "INSN_ACTIVE" # move to "wait completion"
167 # instruction started: must wait till it finishes
168 with m
.State("INSN_ACTIVE"):
169 with m
.If(core
.core_terminated_o
):
170 m
.next
= "IDLE" # back to idle, immediately (OP_ATTN)
172 with m
.If(insn_type
!= MicrOp
.OP_NOP
):
173 comb
+= core_ivalid_i
.eq(1) # instruction is valid
174 comb
+= core_opcode_i
.eq(ilatch
) # actual opcode
175 comb
+= insn_msr
.eq(cur_msr
) # and MSR
176 with m
.If(self
.fast_nia
.wen
):
177 sync
+= pc_changed
.eq(1)
178 with m
.If(~core_busy_o
): # instruction done!
179 # ok here we are not reading the branch unit. TODO
180 # this just blithely overwrites whatever pipeline
182 with m
.If(~pc_changed
):
183 comb
+= self
.fast_w_pc
.wen
.eq(1<<FastRegs
.PC
)
184 comb
+= self
.fast_w_pc
.data_i
.eq(nia
)
185 m
.next
= "IDLE" # back to idle
190 yield from self
.pc_i
.ports()
194 yield from self
.core
.ports()
195 yield from self
.imem
.ports()
201 if __name__
== '__main__':
202 units
= {'alu': 1, 'cr': 1, 'branch': 1, 'trap': 1, 'logical': 1,
206 pspec
= TestMemPspec(ldst_ifacetype
='bare_wb',
207 imem_ifacetype
='bare_wb',
212 dut
= TestIssuer(pspec
)
213 vl
= main(dut
, ports
=dut
.ports(), name
="test_issuer")
215 if len(sys
.argv
) == 1:
216 vl
= rtlil
.convert(dut
, ports
=dut
.ports(), name
="test_issuer")
217 with
open("test_issuer.il", "w") as f
: