7c86bc9d90bd176ade68ae9e6e0f835c2d0ab92a
3 not in any way intended for production use. this runs a FSM that:
5 * reads the Program Counter from StateRegs
6 * reads an instruction from a fixed-size Test Memory
7 * issues it to the Simple Core
8 * waits for it to complete
10 * does it all over again
12 the purpose of this module is to verify the functional correctness
13 of the Function Units in the absolute simplest and clearest possible
14 way, and to at provide something that can be further incrementally
18 from nmigen
import (Elaboratable
, Module
, Signal
, ClockSignal
, ResetSignal
,
19 ClockDomain
, DomainRenamer
, Mux
, Const
, Repl
, Cat
)
20 from nmigen
.cli
import rtlil
21 from nmigen
.cli
import main
24 from nmutil
.singlepipe
import ControlBase
25 from soc
.simple
.core_data
import FetchOutput
, FetchInput
27 from nmigen
.lib
.coding
import PriorityEncoder
29 from openpower
.decoder
.power_decoder
import create_pdecode
30 from openpower
.decoder
.power_decoder2
import PowerDecode2
, SVP64PrefixDecoder
31 from openpower
.decoder
.decode2execute1
import IssuerDecode2ToOperand
32 from openpower
.decoder
.decode2execute1
import Data
33 from openpower
.decoder
.power_enums
import (MicrOp
, SVP64PredInt
, SVP64PredCR
,
35 from openpower
.state
import CoreState
36 from openpower
.consts
import (CR
, SVP64CROffs
, MSR
)
37 from soc
.experiment
.testmem
import TestMemory
# test only for instructions
38 from soc
.regfile
.regfiles
import StateRegs
, FastRegs
39 from soc
.simple
.core
import NonProductionCore
40 from soc
.config
.test
.test_loadstore
import TestMemPspec
41 from soc
.config
.ifetch
import ConfigFetchUnit
42 from soc
.debug
.dmi
import CoreDebug
, DMIInterface
43 from soc
.debug
.jtag
import JTAG
44 from soc
.config
.pinouts
import get_pinspecs
45 from soc
.interrupts
.xics
import XICS_ICP
, XICS_ICS
46 from soc
.bus
.simple_gpio
import SimpleGPIO
47 from soc
.bus
.SPBlock512W64B8W
import SPBlock512W64B8W
48 from soc
.clock
.select
import ClockSelect
49 from soc
.clock
.dummypll
import DummyPLL
50 from openpower
.sv
.svstate
import SVSTATERec
51 from soc
.experiment
.icache
import ICache
53 from nmutil
.util
import rising_edge
56 def get_insn(f_instr_o
, pc
):
57 if f_instr_o
.width
== 32:
60 # 64-bit: bit 2 of pc decides which word to select
61 return f_instr_o
.word_select(pc
[2], 32)
63 # gets state input or reads from state regfile
66 def state_get(m
, res
, core_rst
, state_i
, name
, regfile
, regnum
):
69 # read the {insert state variable here}
70 res_ok_delay
= Signal(name
="%s_ok_delay" % name
)
72 sync
+= res_ok_delay
.eq(~state_i
.ok
)
73 with m
.If(state_i
.ok
):
74 # incoming override (start from pc_i)
75 comb
+= res
.eq(state_i
.data
)
77 # otherwise read StateRegs regfile for {insert state here}...
78 comb
+= regfile
.ren
.eq(1 << regnum
)
79 # ... but on a 1-clock delay
80 with m
.If(res_ok_delay
):
81 comb
+= res
.eq(regfile
.o_data
)
84 def get_predint(m
, mask
, name
):
85 """decode SVP64 predicate integer mask field to reg number and invert
86 this is identical to the equivalent function in ISACaller except that
87 it doesn't read the INT directly, it just decodes "what needs to be done"
88 i.e. which INT reg, whether it is shifted and whether it is bit-inverted.
90 * all1s is set to indicate that no mask is to be applied.
91 * regread indicates the GPR register number to be read
92 * invert is set to indicate that the register value is to be inverted
93 * unary indicates that the contents of the register is to be shifted 1<<r3
96 regread
= Signal(5, name
=name
+"regread")
97 invert
= Signal(name
=name
+"invert")
98 unary
= Signal(name
=name
+"unary")
99 all1s
= Signal(name
=name
+"all1s")
101 with m
.Case(SVP64PredInt
.ALWAYS
.value
):
102 comb
+= all1s
.eq(1) # use 0b1111 (all ones)
103 with m
.Case(SVP64PredInt
.R3_UNARY
.value
):
104 comb
+= regread
.eq(3)
105 comb
+= unary
.eq(1) # 1<<r3 - shift r3 (single bit)
106 with m
.Case(SVP64PredInt
.R3
.value
):
107 comb
+= regread
.eq(3)
108 with m
.Case(SVP64PredInt
.R3_N
.value
):
109 comb
+= regread
.eq(3)
111 with m
.Case(SVP64PredInt
.R10
.value
):
112 comb
+= regread
.eq(10)
113 with m
.Case(SVP64PredInt
.R10_N
.value
):
114 comb
+= regread
.eq(10)
116 with m
.Case(SVP64PredInt
.R30
.value
):
117 comb
+= regread
.eq(30)
118 with m
.Case(SVP64PredInt
.R30_N
.value
):
119 comb
+= regread
.eq(30)
121 return regread
, invert
, unary
, all1s
124 def get_predcr(m
, mask
, name
):
125 """decode SVP64 predicate CR to reg number field and invert status
126 this is identical to _get_predcr in ISACaller
129 idx
= Signal(2, name
=name
+"idx")
130 invert
= Signal(name
=name
+"crinvert")
132 with m
.Case(SVP64PredCR
.LT
.value
):
133 comb
+= idx
.eq(CR
.LT
)
135 with m
.Case(SVP64PredCR
.GE
.value
):
136 comb
+= idx
.eq(CR
.LT
)
138 with m
.Case(SVP64PredCR
.GT
.value
):
139 comb
+= idx
.eq(CR
.GT
)
141 with m
.Case(SVP64PredCR
.LE
.value
):
142 comb
+= idx
.eq(CR
.GT
)
144 with m
.Case(SVP64PredCR
.EQ
.value
):
145 comb
+= idx
.eq(CR
.EQ
)
147 with m
.Case(SVP64PredCR
.NE
.value
):
148 comb
+= idx
.eq(CR
.EQ
)
150 with m
.Case(SVP64PredCR
.SO
.value
):
151 comb
+= idx
.eq(CR
.SO
)
153 with m
.Case(SVP64PredCR
.NS
.value
):
154 comb
+= idx
.eq(CR
.SO
)
159 class TestIssuerBase(Elaboratable
):
160 """TestIssuerBase - common base class for Issuers
162 takes care of power-on reset, peripherals, debug, DEC/TB,
163 and gets PC/MSR/SVSTATE from the State Regfile etc.
166 def __init__(self
, pspec
):
168 # test if microwatt compatibility is to be enabled
169 self
.microwatt_compat
= (hasattr(pspec
, "microwatt_compat") and
170 (pspec
.microwatt_compat
== True))
171 self
.alt_reset
= Signal(reset_less
=True) # not connected yet (microwatt)
173 # test is SVP64 is to be enabled
174 self
.svp64_en
= hasattr(pspec
, "svp64") and (pspec
.svp64
== True)
176 # and if regfiles are reduced
177 self
.regreduce_en
= (hasattr(pspec
, "regreduce") and
178 (pspec
.regreduce
== True))
180 # and if overlap requested
181 self
.allow_overlap
= (hasattr(pspec
, "allow_overlap") and
182 (pspec
.allow_overlap
== True))
184 # and get the core domain
185 self
.core_domain
= "coresync"
186 if (hasattr(pspec
, "core_domain") and
187 isinstance(pspec
.core_domain
, str)):
188 self
.core_domain
= pspec
.core_domain
190 # JTAG interface. add this right at the start because if it's
191 # added it *modifies* the pspec, by adding enable/disable signals
192 # for parts of the rest of the core
193 self
.jtag_en
= hasattr(pspec
, "debug") and pspec
.debug
== 'jtag'
194 #self.dbg_domain = "sync" # sigh "dbgsunc" too problematic
195 self
.dbg_domain
= "dbgsync" # domain for DMI/JTAG clock
197 # XXX MUST keep this up-to-date with litex, and
198 # soc-cocotb-sim, and err.. all needs sorting out, argh
201 'eint', 'gpio', 'mspi0',
202 # 'mspi1', - disabled for now
203 # 'pwm', 'sd0', - disabled for now
205 self
.jtag
= JTAG(get_pinspecs(subset
=subset
),
206 domain
=self
.dbg_domain
)
207 # add signals to pspec to enable/disable icache and dcache
208 # (or data and intstruction wishbone if icache/dcache not included)
209 # https://bugs.libre-soc.org/show_bug.cgi?id=520
210 # TODO: do we actually care if these are not domain-synchronised?
211 # honestly probably not.
212 pspec
.wb_icache_en
= self
.jtag
.wb_icache_en
213 pspec
.wb_dcache_en
= self
.jtag
.wb_dcache_en
214 self
.wb_sram_en
= self
.jtag
.wb_sram_en
216 self
.wb_sram_en
= Const(1)
218 # add 4k sram blocks?
219 self
.sram4x4k
= (hasattr(pspec
, "sram4x4kblock") and
220 pspec
.sram4x4kblock
== True)
224 self
.sram4k
.append(SPBlock512W64B8W(name
="sram4k_%d" % i
,
228 # add interrupt controller?
229 self
.xics
= hasattr(pspec
, "xics") and pspec
.xics
== True
231 self
.xics_icp
= XICS_ICP()
232 self
.xics_ics
= XICS_ICS()
233 self
.int_level_i
= self
.xics_ics
.int_level_i
235 self
.ext_irq
= Signal()
237 # add GPIO peripheral?
238 self
.gpio
= hasattr(pspec
, "gpio") and pspec
.gpio
== True
240 self
.simple_gpio
= SimpleGPIO()
241 self
.gpio_o
= self
.simple_gpio
.gpio_o
243 # main instruction core. suitable for prototyping / demo only
244 self
.core
= core
= NonProductionCore(pspec
)
245 self
.core_rst
= ResetSignal(self
.core_domain
)
247 # instruction decoder. goes into Trap Record
248 #pdecode = create_pdecode()
249 self
.cur_state
= CoreState("cur") # current state (MSR/PC/SVSTATE)
250 self
.pdecode2
= PowerDecode2(None, state
=self
.cur_state
,
251 opkls
=IssuerDecode2ToOperand
,
252 svp64_en
=self
.svp64_en
,
253 regreduce_en
=self
.regreduce_en
)
254 pdecode
= self
.pdecode2
.dec
257 self
.svp64
= SVP64PrefixDecoder() # for decoding SVP64 prefix
259 self
.update_svstate
= Signal() # set this if updating svstate
260 self
.new_svstate
= new_svstate
= SVSTATERec("new_svstate")
262 # Test Instruction memory
263 if hasattr(core
, "icache"):
264 # XXX BLECH! use pspec to transfer the I-Cache to ConfigFetchUnit
265 # truly dreadful. needs a huge reorg.
266 pspec
.icache
= core
.icache
267 self
.imem
= ConfigFetchUnit(pspec
).fu
270 self
.dbg
= CoreDebug()
271 self
.dbg_rst_i
= Signal(reset_less
=True)
273 # instruction go/monitor
274 self
.pc_o
= Signal(64, reset_less
=True)
275 self
.pc_i
= Data(64, "pc_i") # set "ok" to indicate "please change me"
276 self
.msr_i
= Data(64, "msr_i") # set "ok" to indicate "please change me"
277 self
.svstate_i
= Data(64, "svstate_i") # ditto
278 self
.core_bigendian_i
= Signal() # TODO: set based on MSR.LE
279 self
.busy_o
= Signal(reset_less
=True)
280 self
.memerr_o
= Signal(reset_less
=True)
282 # STATE regfile read /write ports for PC, MSR, SVSTATE
283 staterf
= self
.core
.regs
.rf
['state']
284 self
.state_r_msr
= staterf
.r_ports
['msr'] # MSR rd
285 self
.state_r_pc
= staterf
.r_ports
['cia'] # PC rd
286 self
.state_r_sv
= staterf
.r_ports
['sv'] # SVSTATE rd
288 self
.state_w_msr
= staterf
.w_ports
['d_wr2'] # MSR wr
289 self
.state_w_pc
= staterf
.w_ports
['d_wr1'] # PC wr
290 self
.state_w_sv
= staterf
.w_ports
['sv'] # SVSTATE wr
292 # DMI interface access
293 intrf
= self
.core
.regs
.rf
['int']
294 crrf
= self
.core
.regs
.rf
['cr']
295 xerrf
= self
.core
.regs
.rf
['xer']
296 self
.int_r
= intrf
.r_ports
['dmi'] # INT read
297 self
.cr_r
= crrf
.r_ports
['full_cr_dbg'] # CR read
298 self
.xer_r
= xerrf
.r_ports
['full_xer'] # XER read
302 self
.int_pred
= intrf
.r_ports
['pred'] # INT predicate read
303 self
.cr_pred
= crrf
.r_ports
['cr_pred'] # CR predicate read
305 # hack method of keeping an eye on whether branch/trap set the PC
306 self
.state_nia
= self
.core
.regs
.rf
['state'].w_ports
['nia']
307 self
.state_nia
.wen
.name
= 'state_nia_wen'
309 # pulse to synchronize the simulator at instruction end
310 self
.insn_done
= Signal()
312 # indicate any instruction still outstanding, in execution
313 self
.any_busy
= Signal()
316 # store copies of predicate masks
317 self
.srcmask
= Signal(64)
318 self
.dstmask
= Signal(64)
320 # sigh, the wishbone addresses are not wishbone-compliant in microwatt
321 if self
.microwatt_compat
:
322 self
.ibus_adr
= Signal(32, name
='wishbone_insn_out.adr')
323 self
.dbus_adr
= Signal(32, name
='wishbone_data_out.adr')
325 # add an output of the PC and instruction, and whether it was requested
326 # this is for verilator debug purposes
327 if self
.microwatt_compat
:
328 self
.nia
= Signal(64)
329 self
.msr_o
= Signal(64)
330 self
.nia_req
= Signal(1)
331 self
.insn
= Signal(32)
332 self
.ldst_req
= Signal(1)
333 self
.ldst_addr
= Signal(1)
335 def setup_peripherals(self
, m
):
336 comb
, sync
= m
.d
.comb
, m
.d
.sync
338 # okaaaay so the debug module must be in coresync clock domain
339 # but NOT its reset signal. to cope with this, set every single
340 # submodule explicitly in coresync domain, debug and JTAG
341 # in their own one but using *external* reset.
342 csd
= DomainRenamer(self
.core_domain
)
343 dbd
= DomainRenamer(self
.dbg_domain
)
345 if self
.microwatt_compat
:
346 m
.submodules
.core
= core
= self
.core
348 m
.submodules
.core
= core
= csd(self
.core
)
349 # this _so_ needs sorting out. ICache is added down inside
350 # LoadStore1 and is already a submodule of LoadStore1
351 if not isinstance(self
.imem
, ICache
):
352 m
.submodules
.imem
= imem
= csd(self
.imem
)
353 m
.submodules
.dbg
= dbg
= dbd(self
.dbg
)
355 m
.submodules
.jtag
= jtag
= dbd(self
.jtag
)
356 # TODO: UART2GDB mux, here, from external pin
357 # see https://bugs.libre-soc.org/show_bug.cgi?id=499
358 sync
+= dbg
.dmi
.connect_to(jtag
.dmi
)
360 # fixup the clocks in microwatt-compat mode (but leave resets alone
361 # so that microwatt soc.vhdl can pull a reset on the core or DMI
362 # can do it, just like in TestIssuer)
363 if self
.microwatt_compat
:
364 intclk
= ClockSignal(self
.core_domain
)
365 dbgclk
= ClockSignal(self
.dbg_domain
)
366 if self
.core_domain
!= 'sync':
367 comb
+= intclk
.eq(ClockSignal())
368 if self
.dbg_domain
!= 'sync':
369 comb
+= dbgclk
.eq(ClockSignal())
371 # drop the first 3 bits of the incoming wishbone addresses
372 # this can go if using later versions of microwatt (not now)
373 if self
.microwatt_compat
:
374 ibus
= self
.imem
.ibus
375 dbus
= self
.core
.l0
.cmpi
.wb_bus()
376 comb
+= self
.ibus_adr
.eq(Cat(Const(0, 3), ibus
.adr
))
377 comb
+= self
.dbus_adr
.eq(Cat(Const(0, 3), dbus
.adr
))
378 # microwatt verilator debug purposes
379 pi
= self
.core
.l0
.cmpi
.pi
.pi
380 comb
+= self
.ldst_req
.eq(pi
.addr_ok_o
)
381 comb
+= self
.ldst_addr
.eq(pi
.addr
)
383 cur_state
= self
.cur_state
385 # 4x 4k SRAM blocks. these simply "exist", they get routed in litex
387 for i
, sram
in enumerate(self
.sram4k
):
388 m
.submodules
["sram4k_%d" % i
] = csd(sram
)
389 comb
+= sram
.enable
.eq(self
.wb_sram_en
)
391 # XICS interrupt handler
393 m
.submodules
.xics_icp
= icp
= csd(self
.xics_icp
)
394 m
.submodules
.xics_ics
= ics
= csd(self
.xics_ics
)
395 comb
+= icp
.ics_i
.eq(ics
.icp_o
) # connect ICS to ICP
396 sync
+= cur_state
.eint
.eq(icp
.core_irq_o
) # connect ICP to core
398 sync
+= cur_state
.eint
.eq(self
.ext_irq
) # connect externally
400 # GPIO test peripheral
402 m
.submodules
.simple_gpio
= simple_gpio
= csd(self
.simple_gpio
)
404 # connect one GPIO output to ICS bit 15 (like in microwatt soc.vhdl)
405 # XXX causes litex ECP5 test to get wrong idea about input and output
406 # (but works with verilator sim *sigh*)
407 # if self.gpio and self.xics:
408 # comb += self.int_level_i[15].eq(simple_gpio.gpio_o[0])
410 # instruction decoder
411 pdecode
= create_pdecode()
412 m
.submodules
.dec2
= pdecode2
= csd(self
.pdecode2
)
414 m
.submodules
.svp64
= svp64
= csd(self
.svp64
)
417 dmi
, d_reg
, d_cr
, d_xer
, = dbg
.dmi
, dbg
.d_gpr
, dbg
.d_cr
, dbg
.d_xer
418 intrf
= self
.core
.regs
.rf
['int']
420 # clock delay power-on reset
421 cd_por
= ClockDomain(reset_less
=True)
422 cd_sync
= ClockDomain()
423 m
.domains
+= cd_por
, cd_sync
424 core_sync
= ClockDomain(self
.core_domain
)
425 if self
.core_domain
!= "sync":
426 m
.domains
+= core_sync
427 if self
.dbg_domain
!= "sync":
428 dbg_sync
= ClockDomain(self
.dbg_domain
)
429 m
.domains
+= dbg_sync
431 ti_rst
= Signal(reset_less
=True)
432 delay
= Signal(range(4), reset
=3)
433 with m
.If(delay
!= 0):
434 m
.d
.por
+= delay
.eq(delay
- 1)
435 comb
+= cd_por
.clk
.eq(ClockSignal())
437 # power-on reset delay
438 core_rst
= ResetSignal(self
.core_domain
)
439 if self
.core_domain
!= "sync":
440 comb
+= ti_rst
.eq(delay
!= 0 | dbg
.core_rst_o |
ResetSignal())
441 comb
+= core_rst
.eq(ti_rst
)
443 with m
.If(delay
!= 0 | dbg
.core_rst_o
):
444 comb
+= core_rst
.eq(1)
446 # connect external reset signal to DMI Reset
447 if self
.dbg_domain
!= "sync":
448 dbg_rst
= ResetSignal(self
.dbg_domain
)
449 comb
+= dbg_rst
.eq(self
.dbg_rst_i
)
451 # busy/halted signals from core
452 core_busy_o
= ~core
.p
.o_ready | core
.n
.o_data
.busy_o
# core is busy
453 comb
+= self
.busy_o
.eq(core_busy_o
)
454 comb
+= pdecode2
.dec
.bigendian
.eq(self
.core_bigendian_i
)
456 # temporary hack: says "go" immediately for both address gen and ST
458 ldst
= core
.fus
.fus
['ldst0']
459 st_go_edge
= rising_edge(m
, ldst
.st
.rel_o
)
460 # link addr-go direct to rel
461 m
.d
.comb
+= ldst
.ad
.go_i
.eq(ldst
.ad
.rel_o
)
462 m
.d
.comb
+= ldst
.st
.go_i
.eq(st_go_edge
) # link store-go to rising rel
464 def do_dmi(self
, m
, dbg
):
465 """deals with DMI debug requests
467 currently only provides read requests for the INT regfile, CR and XER
468 it will later also deal with *writing* to these regfiles.
472 dmi
, d_reg
, d_cr
, d_xer
, = dbg
.dmi
, dbg
.d_gpr
, dbg
.d_cr
, dbg
.d_xer
473 intrf
= self
.core
.regs
.rf
['int']
475 with m
.If(d_reg
.req
): # request for regfile access being made
476 # TODO: error-check this
477 # XXX should this be combinatorial? sync better?
479 comb
+= self
.int_r
.ren
.eq(1 << d_reg
.addr
)
481 comb
+= self
.int_r
.addr
.eq(d_reg
.addr
)
482 comb
+= self
.int_r
.ren
.eq(1)
483 d_reg_delay
= Signal()
484 sync
+= d_reg_delay
.eq(d_reg
.req
)
485 with m
.If(d_reg_delay
):
486 # data arrives one clock later
487 comb
+= d_reg
.data
.eq(self
.int_r
.o_data
)
488 comb
+= d_reg
.ack
.eq(1)
490 # sigh same thing for CR debug
491 with m
.If(d_cr
.req
): # request for regfile access being made
492 comb
+= self
.cr_r
.ren
.eq(0b11111111) # enable all
493 d_cr_delay
= Signal()
494 sync
+= d_cr_delay
.eq(d_cr
.req
)
495 with m
.If(d_cr_delay
):
496 # data arrives one clock later
497 comb
+= d_cr
.data
.eq(self
.cr_r
.o_data
)
498 comb
+= d_cr
.ack
.eq(1)
501 with m
.If(d_xer
.req
): # request for regfile access being made
502 comb
+= self
.xer_r
.ren
.eq(0b111111) # enable all
503 d_xer_delay
= Signal()
504 sync
+= d_xer_delay
.eq(d_xer
.req
)
505 with m
.If(d_xer_delay
):
506 # data arrives one clock later
507 comb
+= d_xer
.data
.eq(self
.xer_r
.o_data
)
508 comb
+= d_xer
.ack
.eq(1)
510 def tb_dec_fsm(self
, m
, spr_dec
):
513 this is a FSM for updating either dec or tb. it runs alternately
514 DEC, TB, DEC, TB. note that SPR pipeline could have written a new
515 value to DEC, however the regfile has "passthrough" on it so this
518 see v3.0B p1097-1099 for Timeer Resource and p1065 and p1076
521 comb
, sync
= m
.d
.comb
, m
.d
.sync
522 fast_rf
= self
.core
.regs
.rf
['fast']
523 fast_r_dectb
= fast_rf
.r_ports
['issue'] # DEC/TB
524 fast_w_dectb
= fast_rf
.w_ports
['issue'] # DEC/TB
528 # initiates read of current DEC
529 with m
.State("DEC_READ"):
530 comb
+= fast_r_dectb
.addr
.eq(FastRegs
.DEC
)
531 comb
+= fast_r_dectb
.ren
.eq(1)
534 # waits for DEC read to arrive (1 cycle), updates with new value
535 with m
.State("DEC_WRITE"):
537 # TODO: MSR.LPCR 32-bit decrement mode
538 comb
+= new_dec
.eq(fast_r_dectb
.o_data
- 1)
539 comb
+= fast_w_dectb
.addr
.eq(FastRegs
.DEC
)
540 comb
+= fast_w_dectb
.wen
.eq(1)
541 comb
+= fast_w_dectb
.i_data
.eq(new_dec
)
542 sync
+= spr_dec
.eq(new_dec
) # copy into cur_state for decoder
545 # initiates read of current TB
546 with m
.State("TB_READ"):
547 comb
+= fast_r_dectb
.addr
.eq(FastRegs
.TB
)
548 comb
+= fast_r_dectb
.ren
.eq(1)
551 # waits for read TB to arrive, initiates write of current TB
552 with m
.State("TB_WRITE"):
554 comb
+= new_tb
.eq(fast_r_dectb
.o_data
+ 1)
555 comb
+= fast_w_dectb
.addr
.eq(FastRegs
.TB
)
556 comb
+= fast_w_dectb
.wen
.eq(1)
557 comb
+= fast_w_dectb
.i_data
.eq(new_tb
)
562 def elaborate(self
, platform
):
565 comb
, sync
= m
.d
.comb
, m
.d
.sync
566 cur_state
= self
.cur_state
567 pdecode2
= self
.pdecode2
570 # set up peripherals and core
571 core_rst
= self
.core_rst
572 self
.setup_peripherals(m
)
574 # reset current state if core reset requested
576 m
.d
.sync
+= self
.cur_state
.eq(0)
578 # check halted condition: requested PC to execute matches DMI stop addr
579 # and immediately stop. address of 0xffff_ffff_ffff_ffff can never
582 comb
+= halted
.eq(dbg
.stop_addr_o
== dbg
.state
.pc
)
584 comb
+= dbg
.core_stopped_i
.eq(1)
585 comb
+= dbg
.terminate_i
.eq(1)
587 # PC and instruction from I-Memory
588 comb
+= self
.pc_o
.eq(cur_state
.pc
)
589 self
.pc_changed
= Signal() # note write to PC
590 self
.msr_changed
= Signal() # note write to MSR
591 self
.sv_changed
= Signal() # note write to SVSTATE
593 # read state either from incoming override or from regfile
594 state
= CoreState("get") # current state (MSR/PC/SVSTATE)
595 state_get(m
, state
.msr
, core_rst
, self
.msr_i
,
597 self
.state_r_msr
, StateRegs
.MSR
)
598 state_get(m
, state
.pc
, core_rst
, self
.pc_i
,
600 self
.state_r_pc
, StateRegs
.PC
)
601 state_get(m
, state
.svstate
, core_rst
, self
.svstate_i
,
602 "svstate", # read SVSTATE
603 self
.state_r_sv
, StateRegs
.SVSTATE
)
605 # don't write pc every cycle
606 comb
+= self
.state_w_pc
.wen
.eq(0)
607 comb
+= self
.state_w_pc
.i_data
.eq(0)
609 # connect up debug state. note "combinatorially same" below,
610 # this is a bit naff, passing state over in the dbg class, but
611 # because it is combinatorial it achieves the desired goal
612 comb
+= dbg
.state
.eq(state
)
614 # this bit doesn't have to be in the FSM: connect up to read
615 # regfiles on demand from DMI
618 # DEC and TB inc/dec FSM. copy of DEC is put into CoreState,
619 # (which uses that in PowerDecoder2 to raise 0x900 exception)
620 self
.tb_dec_fsm(m
, cur_state
.dec
)
622 # while stopped, allow updating the MSR, PC and SVSTATE.
623 # these are mainly for debugging purposes (including DMI/JTAG)
624 with m
.If(dbg
.core_stopped_i
):
625 with m
.If(self
.pc_i
.ok
):
626 comb
+= self
.state_w_pc
.wen
.eq(1 << StateRegs
.PC
)
627 comb
+= self
.state_w_pc
.i_data
.eq(self
.pc_i
.data
)
628 sync
+= self
.pc_changed
.eq(1)
629 with m
.If(self
.msr_i
.ok
):
630 comb
+= self
.state_w_msr
.wen
.eq(1 << StateRegs
.MSR
)
631 comb
+= self
.state_w_msr
.i_data
.eq(self
.msr_i
.data
)
632 sync
+= self
.msr_changed
.eq(1)
633 with m
.If(self
.svstate_i
.ok | self
.update_svstate
):
634 with m
.If(self
.svstate_i
.ok
): # over-ride from external source
635 comb
+= self
.new_svstate
.eq(self
.svstate_i
.data
)
636 comb
+= self
.state_w_sv
.wen
.eq(1 << StateRegs
.SVSTATE
)
637 comb
+= self
.state_w_sv
.i_data
.eq(self
.new_svstate
)
638 sync
+= self
.sv_changed
.eq(1)
640 # start renaming some of the ports to match microwatt
641 if self
.microwatt_compat
:
642 self
.core
.o
.core_terminate_o
.name
= "terminated_out"
643 # names of DMI interface
644 self
.dbg
.dmi
.addr_i
.name
= 'dmi_addr'
645 self
.dbg
.dmi
.din
.name
= 'dmi_din'
646 self
.dbg
.dmi
.dout
.name
= 'dmi_dout'
647 self
.dbg
.dmi
.req_i
.name
= 'dmi_req'
648 self
.dbg
.dmi
.we_i
.name
= 'dmi_wr'
649 self
.dbg
.dmi
.ack_o
.name
= 'dmi_ack'
650 # wishbone instruction bus
651 ibus
= self
.imem
.ibus
652 ibus
.adr
.name
= 'wishbone_insn_out.adr'
653 ibus
.dat_w
.name
= 'wishbone_insn_out.dat'
654 ibus
.sel
.name
= 'wishbone_insn_out.sel'
655 ibus
.cyc
.name
= 'wishbone_insn_out.cyc'
656 ibus
.stb
.name
= 'wishbone_insn_out.stb'
657 ibus
.we
.name
= 'wishbone_insn_out.we'
658 ibus
.dat_r
.name
= 'wishbone_insn_in.dat'
659 ibus
.ack
.name
= 'wishbone_insn_in.ack'
660 ibus
.stall
.name
= 'wishbone_insn_in.stall'
662 dbus
= self
.core
.l0
.cmpi
.wb_bus()
663 dbus
.adr
.name
= 'wishbone_data_out.adr'
664 dbus
.dat_w
.name
= 'wishbone_data_out.dat'
665 dbus
.sel
.name
= 'wishbone_data_out.sel'
666 dbus
.cyc
.name
= 'wishbone_data_out.cyc'
667 dbus
.stb
.name
= 'wishbone_data_out.stb'
668 dbus
.we
.name
= 'wishbone_data_out.we'
669 dbus
.dat_r
.name
= 'wishbone_data_in.dat'
670 dbus
.ack
.name
= 'wishbone_data_in.ack'
671 dbus
.stall
.name
= 'wishbone_data_in.stall'
676 yield from self
.pc_i
.ports()
677 yield from self
.msr_i
.ports()
680 yield from self
.core
.ports()
681 yield from self
.imem
.ports()
682 yield self
.core_bigendian_i
688 def external_ports(self
):
689 if self
.microwatt_compat
:
690 ports
= [self
.core
.o
.core_terminate_o
,
692 self
.alt_reset
, # not connected yet
693 self
.nia
, self
.insn
, self
.nia_req
, self
.msr_o
,
694 self
.ldst_req
, self
.ldst_addr
,
698 ports
+= list(self
.dbg
.dmi
.ports())
699 # for dbus/ibus microwatt, exclude err btw and cti
700 for name
, sig
in self
.imem
.ibus
.fields
.items():
701 if name
not in ['err', 'bte', 'cti', 'adr']:
703 for name
, sig
in self
.core
.l0
.cmpi
.wb_bus().fields
.items():
704 if name
not in ['err', 'bte', 'cti', 'adr']:
706 # microwatt non-compliant with wishbone
707 ports
.append(self
.ibus_adr
)
708 ports
.append(self
.dbus_adr
)
711 ports
= self
.pc_i
.ports()
712 ports
= self
.msr_i
.ports()
713 ports
+= [self
.pc_o
, self
.memerr_o
, self
.core_bigendian_i
, self
.busy_o
,
717 ports
+= list(self
.jtag
.external_ports())
719 # don't add DMI if JTAG is enabled
720 ports
+= list(self
.dbg
.dmi
.ports())
722 ports
+= list(self
.imem
.ibus
.fields
.values())
723 ports
+= list(self
.core
.l0
.cmpi
.wb_bus().fields
.values())
726 for sram
in self
.sram4k
:
727 ports
+= list(sram
.bus
.fields
.values())
730 ports
+= list(self
.xics_icp
.bus
.fields
.values())
731 ports
+= list(self
.xics_ics
.bus
.fields
.values())
732 ports
.append(self
.int_level_i
)
734 ports
.append(self
.ext_irq
)
737 ports
+= list(self
.simple_gpio
.bus
.fields
.values())
738 ports
.append(self
.gpio_o
)
746 class TestIssuerInternal(TestIssuerBase
):
747 """TestIssuer - reads instructions from TestMemory and issues them
749 efficiency and speed is not the main goal here: functional correctness
750 and code clarity is. optimisations (which almost 100% interfere with
751 easy understanding) come later.
754 def fetch_fsm(self
, m
, dbg
, core
, pc
, msr
, svstate
, nia
, is_svp64_mode
,
755 fetch_pc_o_ready
, fetch_pc_i_valid
,
756 fetch_insn_o_valid
, fetch_insn_i_ready
):
759 this FSM performs fetch of raw instruction data, partial-decodes
760 it 32-bit at a time to detect SVP64 prefixes, and will optionally
761 read a 2nd 32-bit quantity if that occurs.
765 pdecode2
= self
.pdecode2
766 cur_state
= self
.cur_state
767 dec_opcode_i
= pdecode2
.dec
.raw_opcode_in
# raw opcode
769 # also note instruction fetch failed
770 if hasattr(core
, "icache"):
771 fetch_failed
= core
.icache
.i_out
.fetch_failed
774 fetch_failed
= Const(0, 1)
777 # set priv / virt mode on I-Cache, sigh
778 if isinstance(self
.imem
, ICache
):
779 comb
+= self
.imem
.i_in
.priv_mode
.eq(~msr
[MSR
.PR
])
780 comb
+= self
.imem
.i_in
.virt_mode
.eq(msr
[MSR
.IR
]) # Instr. Redir (VM)
782 with m
.FSM(name
='fetch_fsm'):
785 with m
.State("IDLE"):
786 # fetch allowed if not failed and stopped but not stepping
787 # (see dmi.py for how core_stop_o is generated)
788 with m
.If(~fetch_failed
& ~dbg
.core_stop_o
):
789 comb
+= fetch_pc_o_ready
.eq(1)
790 with m
.If(fetch_pc_i_valid
& ~pdecode2
.instr_fault
792 # instruction allowed to go: start by reading the PC
793 # capture the PC and also drop it into Insn Memory
794 # we have joined a pair of combinatorial memory
795 # lookups together. this is Generally Bad.
796 comb
+= self
.imem
.a_pc_i
.eq(pc
)
797 comb
+= self
.imem
.a_i_valid
.eq(1)
798 comb
+= self
.imem
.f_i_valid
.eq(1)
799 # transfer state to output
800 sync
+= cur_state
.pc
.eq(pc
)
801 sync
+= cur_state
.svstate
.eq(svstate
) # and svstate
802 sync
+= cur_state
.msr
.eq(msr
) # and msr
804 m
.next
= "INSN_READ" # move to "wait for bus" phase
806 # dummy pause to find out why simulation is not keeping up
807 with m
.State("INSN_READ"):
808 # when using "single-step" mode, checking dbg.stopping_o
809 # prevents progress. allow fetch to proceed once started
811 #if self.allow_overlap:
812 # stopping = dbg.stopping_o
814 # stopping: jump back to idle
817 with m
.If(self
.imem
.f_busy_o
&
818 ~pdecode2
.instr_fault
): # zzz...
819 # busy but not fetch failed: stay in wait-read
820 comb
+= self
.imem
.a_pc_i
.eq(pc
)
821 comb
+= self
.imem
.a_i_valid
.eq(1)
822 comb
+= self
.imem
.f_i_valid
.eq(1)
824 # not busy (or fetch failed!): instruction fetched
825 # when fetch failed, the instruction gets ignored
827 if hasattr(core
, "icache"):
828 # blech, icache returns actual instruction
829 insn
= self
.imem
.f_instr_o
831 # but these return raw memory
832 insn
= get_insn(self
.imem
.f_instr_o
, cur_state
.pc
)
835 # decode the SVP64 prefix, if any
836 comb
+= svp64
.raw_opcode_in
.eq(insn
)
837 comb
+= svp64
.bigendian
.eq(self
.core_bigendian_i
)
838 # pass the decoded prefix (if any) to PowerDecoder2
839 sync
+= pdecode2
.sv_rm
.eq(svp64
.svp64_rm
)
840 sync
+= pdecode2
.is_svp64_mode
.eq(is_svp64_mode
)
841 # remember whether this is a prefixed instruction,
842 # so the FSM can readily loop when VL==0
843 sync
+= is_svp64_mode
.eq(svp64
.is_svp64_mode
)
844 # calculate the address of the following instruction
845 insn_size
= Mux(svp64
.is_svp64_mode
, 8, 4)
846 sync
+= nia
.eq(cur_state
.pc
+ insn_size
)
847 with m
.If(~svp64
.is_svp64_mode
):
848 # with no prefix, store the instruction
849 # and hand it directly to the next FSM
850 sync
+= dec_opcode_i
.eq(insn
)
851 m
.next
= "INSN_READY"
853 # fetch the rest of the instruction from memory
854 comb
+= self
.imem
.a_pc_i
.eq(cur_state
.pc
+ 4)
855 comb
+= self
.imem
.a_i_valid
.eq(1)
856 comb
+= self
.imem
.f_i_valid
.eq(1)
857 m
.next
= "INSN_READ2"
859 # not SVP64 - 32-bit only
860 sync
+= nia
.eq(cur_state
.pc
+ 4)
861 sync
+= dec_opcode_i
.eq(insn
)
862 if self
.microwatt_compat
:
863 # for verilator debug purposes
864 comb
+= self
.insn
.eq(insn
)
865 comb
+= self
.nia
.eq(cur_state
.pc
)
866 comb
+= self
.msr_o
.eq(cur_state
.msr
)
867 comb
+= self
.nia_req
.eq(1)
868 m
.next
= "INSN_READY"
870 with m
.State("INSN_READ2"):
871 with m
.If(self
.imem
.f_busy_o
): # zzz...
872 # busy: stay in wait-read
873 comb
+= self
.imem
.a_i_valid
.eq(1)
874 comb
+= self
.imem
.f_i_valid
.eq(1)
876 # not busy: instruction fetched
877 if hasattr(core
, "icache"):
878 # blech, icache returns actual instruction
879 insn
= self
.imem
.f_instr_o
881 insn
= get_insn(self
.imem
.f_instr_o
, cur_state
.pc
+4)
882 sync
+= dec_opcode_i
.eq(insn
)
883 m
.next
= "INSN_READY"
884 # TODO: probably can start looking at pdecode2.rm_dec
885 # here or maybe even in INSN_READ state, if svp64_mode
886 # detected, in order to trigger - and wait for - the
889 pmode
= pdecode2
.rm_dec
.predmode
891 if pmode != SVP64PredMode.ALWAYS.value:
892 fire predicate loading FSM and wait before
895 sync += self.srcmask.eq(-1) # set to all 1s
896 sync += self.dstmask.eq(-1) # set to all 1s
897 m.next = "INSN_READY"
900 with m
.State("INSN_READY"):
901 # hand over the instruction, to be decoded
902 comb
+= fetch_insn_o_valid
.eq(1)
903 with m
.If(fetch_insn_i_ready
):
907 def fetch_predicate_fsm(self
, m
,
908 pred_insn_i_valid
, pred_insn_o_ready
,
909 pred_mask_o_valid
, pred_mask_i_ready
):
910 """fetch_predicate_fsm - obtains (constructs in the case of CR)
911 src/dest predicate masks
913 https://bugs.libre-soc.org/show_bug.cgi?id=617
914 the predicates can be read here, by using IntRegs r_ports['pred']
915 or CRRegs r_ports['pred']. in the case of CRs it will have to
916 be done through multiple reads, extracting one relevant at a time.
917 later, a faster way would be to use the 32-bit-wide CR port but
918 this is more complex decoding, here. equivalent code used in
919 ISACaller is "from openpower.decoder.isa.caller import get_predcr"
921 note: this ENTIRE FSM is not to be called when svp64 is disabled
925 pdecode2
= self
.pdecode2
926 rm_dec
= pdecode2
.rm_dec
# SVP64RMModeDecode
927 predmode
= rm_dec
.predmode
928 srcpred
, dstpred
= rm_dec
.srcpred
, rm_dec
.dstpred
929 cr_pred
, int_pred
= self
.cr_pred
, self
.int_pred
# read regfiles
930 # get src/dst step, so we can skip already used mask bits
931 cur_state
= self
.cur_state
932 srcstep
= cur_state
.svstate
.srcstep
933 dststep
= cur_state
.svstate
.dststep
934 cur_vl
= cur_state
.svstate
.vl
937 sregread
, sinvert
, sunary
, sall1s
= get_predint(m
, srcpred
, 's')
938 dregread
, dinvert
, dunary
, dall1s
= get_predint(m
, dstpred
, 'd')
939 sidx
, scrinvert
= get_predcr(m
, srcpred
, 's')
940 didx
, dcrinvert
= get_predcr(m
, dstpred
, 'd')
942 # store fetched masks, for either intpred or crpred
943 # when src/dst step is not zero, the skipped mask bits need to be
944 # shifted-out, before actually storing them in src/dest mask
945 new_srcmask
= Signal(64, reset_less
=True)
946 new_dstmask
= Signal(64, reset_less
=True)
948 with m
.FSM(name
="fetch_predicate"):
950 with m
.State("FETCH_PRED_IDLE"):
951 comb
+= pred_insn_o_ready
.eq(1)
952 with m
.If(pred_insn_i_valid
):
953 with m
.If(predmode
== SVP64PredMode
.INT
):
954 # skip fetching destination mask register, when zero
956 sync
+= new_dstmask
.eq(-1)
957 # directly go to fetch source mask register
958 # guaranteed not to be zero (otherwise predmode
959 # would be SVP64PredMode.ALWAYS, not INT)
960 comb
+= int_pred
.addr
.eq(sregread
)
961 comb
+= int_pred
.ren
.eq(1)
962 m
.next
= "INT_SRC_READ"
963 # fetch destination predicate register
965 comb
+= int_pred
.addr
.eq(dregread
)
966 comb
+= int_pred
.ren
.eq(1)
967 m
.next
= "INT_DST_READ"
968 with m
.Elif(predmode
== SVP64PredMode
.CR
):
969 # go fetch masks from the CR register file
970 sync
+= new_srcmask
.eq(0)
971 sync
+= new_dstmask
.eq(0)
974 sync
+= self
.srcmask
.eq(-1)
975 sync
+= self
.dstmask
.eq(-1)
976 m
.next
= "FETCH_PRED_DONE"
978 with m
.State("INT_DST_READ"):
979 # store destination mask
980 inv
= Repl(dinvert
, 64)
982 # set selected mask bit for 1<<r3 mode
983 dst_shift
= Signal(range(64))
984 comb
+= dst_shift
.eq(self
.int_pred
.o_data
& 0b111111)
985 sync
+= new_dstmask
.eq(1 << dst_shift
)
987 # invert mask if requested
988 sync
+= new_dstmask
.eq(self
.int_pred
.o_data ^ inv
)
989 # skip fetching source mask register, when zero
991 sync
+= new_srcmask
.eq(-1)
992 m
.next
= "FETCH_PRED_SHIFT_MASK"
993 # fetch source predicate register
995 comb
+= int_pred
.addr
.eq(sregread
)
996 comb
+= int_pred
.ren
.eq(1)
997 m
.next
= "INT_SRC_READ"
999 with m
.State("INT_SRC_READ"):
1001 inv
= Repl(sinvert
, 64)
1003 # set selected mask bit for 1<<r3 mode
1004 src_shift
= Signal(range(64))
1005 comb
+= src_shift
.eq(self
.int_pred
.o_data
& 0b111111)
1006 sync
+= new_srcmask
.eq(1 << src_shift
)
1008 # invert mask if requested
1009 sync
+= new_srcmask
.eq(self
.int_pred
.o_data ^ inv
)
1010 m
.next
= "FETCH_PRED_SHIFT_MASK"
1012 # fetch masks from the CR register file
1013 # implements the following loop:
1014 # idx, inv = get_predcr(mask)
1016 # for cr_idx in range(vl):
1017 # cr = crl[cr_idx + SVP64CROffs.CRPred] # takes one cycle
1019 # mask |= 1 << cr_idx
1021 with m
.State("CR_READ"):
1022 # CR index to be read, which will be ready by the next cycle
1023 cr_idx
= Signal
.like(cur_vl
, reset_less
=True)
1024 # submit the read operation to the regfile
1025 with m
.If(cr_idx
!= cur_vl
):
1026 # the CR read port is unary ...
1028 # ... in MSB0 convention ...
1029 # ren = 1 << (7 - cr_idx)
1030 # ... and with an offset:
1031 # ren = 1 << (7 - off - cr_idx)
1032 idx
= SVP64CROffs
.CRPred
+ cr_idx
1033 comb
+= cr_pred
.ren
.eq(1 << (7 - idx
))
1034 # signal data valid in the next cycle
1035 cr_read
= Signal(reset_less
=True)
1036 sync
+= cr_read
.eq(1)
1037 # load the next index
1038 sync
+= cr_idx
.eq(cr_idx
+ 1)
1041 sync
+= cr_read
.eq(0)
1042 sync
+= cr_idx
.eq(0)
1043 m
.next
= "FETCH_PRED_SHIFT_MASK"
1045 # compensate for the one cycle delay on the regfile
1046 cur_cr_idx
= Signal
.like(cur_vl
)
1047 comb
+= cur_cr_idx
.eq(cr_idx
- 1)
1048 # read the CR field, select the appropriate bit
1049 cr_field
= Signal(4)
1052 comb
+= cr_field
.eq(cr_pred
.o_data
)
1053 comb
+= scr_bit
.eq(cr_field
.bit_select(sidx
, 1)
1055 comb
+= dcr_bit
.eq(cr_field
.bit_select(didx
, 1)
1057 # set the corresponding mask bit
1058 bit_to_set
= Signal
.like(self
.srcmask
)
1059 comb
+= bit_to_set
.eq(1 << cur_cr_idx
)
1061 sync
+= new_srcmask
.eq(new_srcmask | bit_to_set
)
1063 sync
+= new_dstmask
.eq(new_dstmask | bit_to_set
)
1065 with m
.State("FETCH_PRED_SHIFT_MASK"):
1066 # shift-out skipped mask bits
1067 sync
+= self
.srcmask
.eq(new_srcmask
>> srcstep
)
1068 sync
+= self
.dstmask
.eq(new_dstmask
>> dststep
)
1069 m
.next
= "FETCH_PRED_DONE"
1071 with m
.State("FETCH_PRED_DONE"):
1072 comb
+= pred_mask_o_valid
.eq(1)
1073 with m
.If(pred_mask_i_ready
):
1074 m
.next
= "FETCH_PRED_IDLE"
1076 def issue_fsm(self
, m
, core
, nia
,
1077 dbg
, core_rst
, is_svp64_mode
,
1078 fetch_pc_o_ready
, fetch_pc_i_valid
,
1079 fetch_insn_o_valid
, fetch_insn_i_ready
,
1080 pred_insn_i_valid
, pred_insn_o_ready
,
1081 pred_mask_o_valid
, pred_mask_i_ready
,
1082 exec_insn_i_valid
, exec_insn_o_ready
,
1083 exec_pc_o_valid
, exec_pc_i_ready
):
1086 decode / issue FSM. this interacts with the "fetch" FSM
1087 through fetch_insn_ready/valid (incoming) and fetch_pc_ready/valid
1088 (outgoing). also interacts with the "execute" FSM
1089 through exec_insn_ready/valid (outgoing) and exec_pc_ready/valid
1091 SVP64 RM prefixes have already been set up by the
1092 "fetch" phase, so execute is fairly straightforward.
1097 pdecode2
= self
.pdecode2
1098 cur_state
= self
.cur_state
1099 new_svstate
= self
.new_svstate
1102 dec_opcode_i
= pdecode2
.dec
.raw_opcode_in
# raw opcode
1104 # for updating svstate (things like srcstep etc.)
1105 comb
+= new_svstate
.eq(cur_state
.svstate
)
1107 # precalculate srcstep+1 and dststep+1
1108 cur_srcstep
= cur_state
.svstate
.srcstep
1109 cur_dststep
= cur_state
.svstate
.dststep
1110 next_srcstep
= Signal
.like(cur_srcstep
)
1111 next_dststep
= Signal
.like(cur_dststep
)
1112 comb
+= next_srcstep
.eq(cur_state
.svstate
.srcstep
+1)
1113 comb
+= next_dststep
.eq(cur_state
.svstate
.dststep
+1)
1115 # note if an exception happened. in a pipelined or OoO design
1116 # this needs to be accompanied by "shadowing" (or stalling)
1117 exc_happened
= self
.core
.o
.exc_happened
1118 # also note instruction fetch failed
1119 if hasattr(core
, "icache"):
1120 fetch_failed
= core
.icache
.i_out
.fetch_failed
1122 # set to fault in decoder
1123 # update (highest priority) instruction fault
1124 rising_fetch_failed
= rising_edge(m
, fetch_failed
)
1125 with m
.If(rising_fetch_failed
):
1126 sync
+= pdecode2
.instr_fault
.eq(1)
1128 fetch_failed
= Const(0, 1)
1129 flush_needed
= False
1131 with m
.FSM(name
="issue_fsm"):
1133 # sync with the "fetch" phase which is reading the instruction
1134 # at this point, there is no instruction running, that
1135 # could inadvertently update the PC.
1136 with m
.State("ISSUE_START"):
1137 # reset instruction fault
1138 sync
+= pdecode2
.instr_fault
.eq(0)
1139 # wait on "core stop" release, before next fetch
1140 # need to do this here, in case we are in a VL==0 loop
1141 with m
.If(~dbg
.core_stop_o
& ~core_rst
):
1142 comb
+= fetch_pc_i_valid
.eq(1) # tell fetch to start
1143 with m
.If(fetch_pc_o_ready
): # fetch acknowledged us
1144 m
.next
= "INSN_WAIT"
1146 # tell core it's stopped, and acknowledge debug handshake
1147 comb
+= dbg
.core_stopped_i
.eq(1)
1148 # while stopped, allow updating SVSTATE
1149 with m
.If(self
.svstate_i
.ok
):
1150 comb
+= new_svstate
.eq(self
.svstate_i
.data
)
1151 comb
+= self
.update_svstate
.eq(1)
1152 sync
+= self
.sv_changed
.eq(1)
1154 # wait for an instruction to arrive from Fetch
1155 with m
.State("INSN_WAIT"):
1156 # when using "single-step" mode, checking dbg.stopping_o
1157 # prevents progress. allow issue to proceed once started
1159 #if self.allow_overlap:
1160 # stopping = dbg.stopping_o
1161 with m
.If(stopping
):
1162 # stopping: jump back to idle
1163 m
.next
= "ISSUE_START"
1165 # request the icache to stop asserting "failed"
1166 comb
+= core
.icache
.flush_in
.eq(1)
1167 # stop instruction fault
1168 sync
+= pdecode2
.instr_fault
.eq(0)
1170 comb
+= fetch_insn_i_ready
.eq(1)
1171 with m
.If(fetch_insn_o_valid
):
1172 # loop into ISSUE_START if it's a SVP64 instruction
1173 # and VL == 0. this because VL==0 is a for-loop
1174 # from 0 to 0 i.e. always, always a NOP.
1175 cur_vl
= cur_state
.svstate
.vl
1176 with m
.If(is_svp64_mode
& (cur_vl
== 0)):
1177 # update the PC before fetching the next instruction
1178 # since we are in a VL==0 loop, no instruction was
1179 # executed that we could be overwriting
1180 comb
+= self
.state_w_pc
.wen
.eq(1 << StateRegs
.PC
)
1181 comb
+= self
.state_w_pc
.i_data
.eq(nia
)
1182 comb
+= self
.insn_done
.eq(1)
1183 m
.next
= "ISSUE_START"
1186 m
.next
= "PRED_START" # fetching predicate
1188 m
.next
= "DECODE_SV" # skip predication
1190 with m
.State("PRED_START"):
1191 comb
+= pred_insn_i_valid
.eq(1) # tell fetch_pred to start
1192 with m
.If(pred_insn_o_ready
): # fetch_pred acknowledged us
1193 m
.next
= "MASK_WAIT"
1195 with m
.State("MASK_WAIT"):
1196 comb
+= pred_mask_i_ready
.eq(1) # ready to receive the masks
1197 with m
.If(pred_mask_o_valid
): # predication masks are ready
1198 m
.next
= "PRED_SKIP"
1200 # skip zeros in predicate
1201 with m
.State("PRED_SKIP"):
1202 with m
.If(~is_svp64_mode
):
1203 m
.next
= "DECODE_SV" # nothing to do
1206 pred_src_zero
= pdecode2
.rm_dec
.pred_sz
1207 pred_dst_zero
= pdecode2
.rm_dec
.pred_dz
1209 # new srcstep, after skipping zeros
1210 skip_srcstep
= Signal
.like(cur_srcstep
)
1211 # value to be added to the current srcstep
1212 src_delta
= Signal
.like(cur_srcstep
)
1213 # add leading zeros to srcstep, if not in zero mode
1214 with m
.If(~pred_src_zero
):
1215 # priority encoder (count leading zeros)
1216 # append guard bit, in case the mask is all zeros
1217 pri_enc_src
= PriorityEncoder(65)
1218 m
.submodules
.pri_enc_src
= pri_enc_src
1219 comb
+= pri_enc_src
.i
.eq(Cat(self
.srcmask
,
1221 comb
+= src_delta
.eq(pri_enc_src
.o
)
1222 # apply delta to srcstep
1223 comb
+= skip_srcstep
.eq(cur_srcstep
+ src_delta
)
1224 # shift-out all leading zeros from the mask
1225 # plus the leading "one" bit
1226 # TODO count leading zeros and shift-out the zero
1227 # bits, in the same step, in hardware
1228 sync
+= self
.srcmask
.eq(self
.srcmask
>> (src_delta
+1))
1230 # same as above, but for dststep
1231 skip_dststep
= Signal
.like(cur_dststep
)
1232 dst_delta
= Signal
.like(cur_dststep
)
1233 with m
.If(~pred_dst_zero
):
1234 pri_enc_dst
= PriorityEncoder(65)
1235 m
.submodules
.pri_enc_dst
= pri_enc_dst
1236 comb
+= pri_enc_dst
.i
.eq(Cat(self
.dstmask
,
1238 comb
+= dst_delta
.eq(pri_enc_dst
.o
)
1239 comb
+= skip_dststep
.eq(cur_dststep
+ dst_delta
)
1240 sync
+= self
.dstmask
.eq(self
.dstmask
>> (dst_delta
+1))
1242 # TODO: initialize mask[VL]=1 to avoid passing past VL
1243 with m
.If((skip_srcstep
>= cur_vl
) |
1244 (skip_dststep
>= cur_vl
)):
1245 # end of VL loop. Update PC and reset src/dst step
1246 comb
+= self
.state_w_pc
.wen
.eq(1 << StateRegs
.PC
)
1247 comb
+= self
.state_w_pc
.i_data
.eq(nia
)
1248 comb
+= new_svstate
.srcstep
.eq(0)
1249 comb
+= new_svstate
.dststep
.eq(0)
1250 comb
+= self
.update_svstate
.eq(1)
1251 # synchronize with the simulator
1252 comb
+= self
.insn_done
.eq(1)
1254 m
.next
= "ISSUE_START"
1256 # update new src/dst step
1257 comb
+= new_svstate
.srcstep
.eq(skip_srcstep
)
1258 comb
+= new_svstate
.dststep
.eq(skip_dststep
)
1259 comb
+= self
.update_svstate
.eq(1)
1261 m
.next
= "DECODE_SV"
1263 # pass predicate mask bits through to satellite decoders
1264 # TODO: for SIMD this will be *multiple* bits
1265 sync
+= core
.i
.sv_pred_sm
.eq(self
.srcmask
[0])
1266 sync
+= core
.i
.sv_pred_dm
.eq(self
.dstmask
[0])
1268 # after src/dst step have been updated, we are ready
1269 # to decode the instruction
1270 with m
.State("DECODE_SV"):
1271 # decode the instruction
1272 with m
.If(~fetch_failed
):
1273 sync
+= pdecode2
.instr_fault
.eq(0)
1274 sync
+= core
.i
.e
.eq(pdecode2
.e
)
1275 sync
+= core
.i
.state
.eq(cur_state
)
1276 sync
+= core
.i
.raw_insn_i
.eq(dec_opcode_i
)
1277 sync
+= core
.i
.bigendian_i
.eq(self
.core_bigendian_i
)
1279 sync
+= core
.i
.sv_rm
.eq(pdecode2
.sv_rm
)
1280 # set RA_OR_ZERO detection in satellite decoders
1281 sync
+= core
.i
.sv_a_nz
.eq(pdecode2
.sv_a_nz
)
1282 # and svp64 detection
1283 sync
+= core
.i
.is_svp64_mode
.eq(is_svp64_mode
)
1284 # and svp64 bit-rev'd ldst mode
1285 ldst_dec
= pdecode2
.use_svp64_ldst_dec
1286 sync
+= core
.i
.use_svp64_ldst_dec
.eq(ldst_dec
)
1287 # after decoding, reset any previous exception condition,
1288 # allowing it to be set again during the next execution
1289 sync
+= pdecode2
.ldst_exc
.eq(0)
1291 m
.next
= "INSN_EXECUTE" # move to "execute"
1293 # handshake with execution FSM, move to "wait" once acknowledged
1294 with m
.State("INSN_EXECUTE"):
1295 # when using "single-step" mode, checking dbg.stopping_o
1296 # prevents progress. allow execute to proceed once started
1298 #if self.allow_overlap:
1299 # stopping = dbg.stopping_o
1300 with m
.If(stopping
):
1301 # stopping: jump back to idle
1302 m
.next
= "ISSUE_START"
1304 # request the icache to stop asserting "failed"
1305 comb
+= core
.icache
.flush_in
.eq(1)
1306 # stop instruction fault
1307 sync
+= pdecode2
.instr_fault
.eq(0)
1309 comb
+= exec_insn_i_valid
.eq(1) # trigger execute
1310 with m
.If(exec_insn_o_ready
): # execute acknowledged us
1311 m
.next
= "EXECUTE_WAIT"
1313 with m
.State("EXECUTE_WAIT"):
1314 comb
+= exec_pc_i_ready
.eq(1)
1315 # see https://bugs.libre-soc.org/show_bug.cgi?id=636
1316 # the exception info needs to be blatted into
1317 # pdecode.ldst_exc, and the instruction "re-run".
1318 # when ldst_exc.happened is set, the PowerDecoder2
1319 # reacts very differently: it re-writes the instruction
1320 # with a "trap" (calls PowerDecoder2.trap()) which
1321 # will *overwrite* whatever was requested and jump the
1322 # PC to the exception address, as well as alter MSR.
1323 # nothing else needs to be done other than to note
1324 # the change of PC and MSR (and, later, SVSTATE)
1325 with m
.If(exc_happened
):
1326 mmu
= core
.fus
.get_exc("mmu0")
1327 ldst
= core
.fus
.get_exc("ldst0")
1329 with m
.If(fetch_failed
):
1330 # instruction fetch: exception is from MMU
1331 # reset instr_fault (highest priority)
1332 sync
+= pdecode2
.ldst_exc
.eq(mmu
)
1333 sync
+= pdecode2
.instr_fault
.eq(0)
1335 # request icache to stop asserting "failed"
1336 comb
+= core
.icache
.flush_in
.eq(1)
1337 with m
.If(~fetch_failed
):
1338 # otherwise assume it was a LDST exception
1339 sync
+= pdecode2
.ldst_exc
.eq(ldst
)
1341 with m
.If(exec_pc_o_valid
):
1343 # was this the last loop iteration?
1345 cur_vl
= cur_state
.svstate
.vl
1346 comb
+= is_last
.eq(next_srcstep
== cur_vl
)
1348 with m
.If(pdecode2
.instr_fault
):
1349 # reset instruction fault, try again
1350 sync
+= pdecode2
.instr_fault
.eq(0)
1351 m
.next
= "ISSUE_START"
1353 # return directly to Decode if Execute generated an
1355 with m
.Elif(pdecode2
.ldst_exc
.happened
):
1356 m
.next
= "DECODE_SV"
1358 # if MSR, PC or SVSTATE were changed by the previous
1359 # instruction, go directly back to Fetch, without
1360 # updating either MSR PC or SVSTATE
1361 with m
.Elif(self
.msr_changed | self
.pc_changed |
1363 m
.next
= "ISSUE_START"
1365 # also return to Fetch, when no output was a vector
1366 # (regardless of SRCSTEP and VL), or when the last
1367 # instruction was really the last one of the VL loop
1368 with m
.Elif((~pdecode2
.loop_continue
) | is_last
):
1369 # before going back to fetch, update the PC state
1370 # register with the NIA.
1371 # ok here we are not reading the branch unit.
1372 # TODO: this just blithely overwrites whatever
1373 # pipeline updated the PC
1374 comb
+= self
.state_w_pc
.wen
.eq(1 << StateRegs
.PC
)
1375 comb
+= self
.state_w_pc
.i_data
.eq(nia
)
1376 # reset SRCSTEP before returning to Fetch
1378 with m
.If(pdecode2
.loop_continue
):
1379 comb
+= new_svstate
.srcstep
.eq(0)
1380 comb
+= new_svstate
.dststep
.eq(0)
1381 comb
+= self
.update_svstate
.eq(1)
1383 comb
+= new_svstate
.srcstep
.eq(0)
1384 comb
+= new_svstate
.dststep
.eq(0)
1385 comb
+= self
.update_svstate
.eq(1)
1386 m
.next
= "ISSUE_START"
1388 # returning to Execute? then, first update SRCSTEP
1390 comb
+= new_svstate
.srcstep
.eq(next_srcstep
)
1391 comb
+= new_svstate
.dststep
.eq(next_dststep
)
1392 comb
+= self
.update_svstate
.eq(1)
1393 # return to mask skip loop
1394 m
.next
= "PRED_SKIP"
1397 # check if svstate needs updating: if so, write it to State Regfile
1398 with m
.If(self
.update_svstate
):
1399 sync
+= cur_state
.svstate
.eq(self
.new_svstate
) # for next clock
1401 def execute_fsm(self
, m
, core
,
1402 exec_insn_i_valid
, exec_insn_o_ready
,
1403 exec_pc_o_valid
, exec_pc_i_ready
):
1406 execute FSM. this interacts with the "issue" FSM
1407 through exec_insn_ready/valid (incoming) and exec_pc_ready/valid
1408 (outgoing). SVP64 RM prefixes have already been set up by the
1409 "issue" phase, so execute is fairly straightforward.
1415 pdecode2
= self
.pdecode2
1418 core_busy_o
= core
.n
.o_data
.busy_o
# core is busy
1419 core_ivalid_i
= core
.p
.i_valid
# instruction is valid
1421 if hasattr(core
, "icache"):
1422 fetch_failed
= core
.icache
.i_out
.fetch_failed
1424 fetch_failed
= Const(0, 1)
1426 with m
.FSM(name
="exec_fsm"):
1428 # waiting for instruction bus (stays there until not busy)
1429 with m
.State("INSN_START"):
1430 comb
+= exec_insn_o_ready
.eq(1)
1431 with m
.If(exec_insn_i_valid
):
1432 comb
+= core_ivalid_i
.eq(1) # instruction is valid/issued
1433 sync
+= self
.sv_changed
.eq(0)
1434 sync
+= self
.pc_changed
.eq(0)
1435 sync
+= self
.msr_changed
.eq(0)
1436 with m
.If(core
.p
.o_ready
): # only move if accepted
1437 m
.next
= "INSN_ACTIVE" # move to "wait completion"
1439 # instruction started: must wait till it finishes
1440 with m
.State("INSN_ACTIVE"):
1441 # note changes to MSR, PC and SVSTATE
1442 # XXX oops, really must monitor *all* State Regfile write
1443 # ports looking for changes!
1444 with m
.If(self
.state_nia
.wen
& (1 << StateRegs
.SVSTATE
)):
1445 sync
+= self
.sv_changed
.eq(1)
1446 with m
.If(self
.state_nia
.wen
& (1 << StateRegs
.MSR
)):
1447 sync
+= self
.msr_changed
.eq(1)
1448 with m
.If(self
.state_nia
.wen
& (1 << StateRegs
.PC
)):
1449 sync
+= self
.pc_changed
.eq(1)
1450 with m
.If(~core_busy_o
): # instruction done!
1451 comb
+= exec_pc_o_valid
.eq(1)
1452 with m
.If(exec_pc_i_ready
):
1453 # when finished, indicate "done".
1454 # however, if there was an exception, the instruction
1455 # is *not* yet done. this is an implementation
1456 # detail: we choose to implement exceptions by
1457 # taking the exception information from the LDST
1458 # unit, putting that *back* into the PowerDecoder2,
1459 # and *re-running the entire instruction*.
1460 # if we erroneously indicate "done" here, it is as if
1461 # there were *TWO* instructions:
1462 # 1) the failed LDST 2) a TRAP.
1463 with m
.If(~pdecode2
.ldst_exc
.happened
&
1464 ~pdecode2
.instr_fault
):
1465 comb
+= self
.insn_done
.eq(1)
1466 m
.next
= "INSN_START" # back to fetch
1467 # terminate returns directly to INSN_START
1468 with m
.If(dbg
.terminate_i
):
1469 # comb += self.insn_done.eq(1) - no because it's not
1470 m
.next
= "INSN_START" # back to fetch
1472 def elaborate(self
, platform
):
1473 m
= super().elaborate(platform
)
1475 comb
, sync
= m
.d
.comb
, m
.d
.sync
1476 cur_state
= self
.cur_state
1477 pdecode2
= self
.pdecode2
1481 # set up peripherals and core
1482 core_rst
= self
.core_rst
1484 # indicate to outside world if any FU is still executing
1485 comb
+= self
.any_busy
.eq(core
.n
.o_data
.any_busy_o
) # any FU executing
1487 # address of the next instruction, in the absence of a branch
1488 # depends on the instruction size
1491 # connect up debug signals
1492 with m
.If(core
.o
.core_terminate_o
):
1493 comb
+= dbg
.terminate_i
.eq(1)
1495 # pass the prefix mode from Fetch to Issue, so the latter can loop
1497 is_svp64_mode
= Signal()
1499 # there are *THREE^WFOUR-if-SVP64-enabled* FSMs, fetch (32/64-bit)
1500 # issue, decode/execute, now joined by "Predicate fetch/calculate".
1501 # these are the handshake signals between each
1503 # fetch FSM can run as soon as the PC is valid
1504 fetch_pc_i_valid
= Signal() # Execute tells Fetch "start next read"
1505 fetch_pc_o_ready
= Signal() # Fetch Tells SVSTATE "proceed"
1507 # fetch FSM hands over the instruction to be decoded / issued
1508 fetch_insn_o_valid
= Signal()
1509 fetch_insn_i_ready
= Signal()
1511 # predicate fetch FSM decodes and fetches the predicate
1512 pred_insn_i_valid
= Signal()
1513 pred_insn_o_ready
= Signal()
1515 # predicate fetch FSM delivers the masks
1516 pred_mask_o_valid
= Signal()
1517 pred_mask_i_ready
= Signal()
1519 # issue FSM delivers the instruction to the be executed
1520 exec_insn_i_valid
= Signal()
1521 exec_insn_o_ready
= Signal()
1523 # execute FSM, hands over the PC/SVSTATE back to the issue FSM
1524 exec_pc_o_valid
= Signal()
1525 exec_pc_i_ready
= Signal()
1527 # the FSMs here are perhaps unusual in that they detect conditions
1528 # then "hold" information, combinatorially, for the core
1529 # (as opposed to using sync - which would be on a clock's delay)
1530 # this includes the actual opcode, valid flags and so on.
1532 # Fetch, then predicate fetch, then Issue, then Execute.
1533 # Issue is where the VL for-loop # lives. the ready/valid
1534 # signalling is used to communicate between the four.
1536 self
.fetch_fsm(m
, dbg
, core
, dbg
.state
.pc
, dbg
.state
.msr
,
1537 dbg
.state
.svstate
, nia
, is_svp64_mode
,
1538 fetch_pc_o_ready
, fetch_pc_i_valid
,
1539 fetch_insn_o_valid
, fetch_insn_i_ready
)
1541 self
.issue_fsm(m
, core
, nia
,
1542 dbg
, core_rst
, is_svp64_mode
,
1543 fetch_pc_o_ready
, fetch_pc_i_valid
,
1544 fetch_insn_o_valid
, fetch_insn_i_ready
,
1545 pred_insn_i_valid
, pred_insn_o_ready
,
1546 pred_mask_o_valid
, pred_mask_i_ready
,
1547 exec_insn_i_valid
, exec_insn_o_ready
,
1548 exec_pc_o_valid
, exec_pc_i_ready
)
1551 self
.fetch_predicate_fsm(m
,
1552 pred_insn_i_valid
, pred_insn_o_ready
,
1553 pred_mask_o_valid
, pred_mask_i_ready
)
1555 self
.execute_fsm(m
, core
,
1556 exec_insn_i_valid
, exec_insn_o_ready
,
1557 exec_pc_o_valid
, exec_pc_i_ready
)
1559 # whatever was done above, over-ride it if core reset is held
1560 with m
.If(core_rst
):
1566 class TestIssuer(Elaboratable
):
1567 def __init__(self
, pspec
):
1568 self
.ti
= TestIssuerInternal(pspec
)
1569 self
.pll
= DummyPLL(instance
=True)
1571 self
.dbg_rst_i
= Signal(reset_less
=True)
1573 # PLL direct clock or not
1574 self
.pll_en
= hasattr(pspec
, "use_pll") and pspec
.use_pll
1576 self
.pll_test_o
= Signal(reset_less
=True)
1577 self
.pll_vco_o
= Signal(reset_less
=True)
1578 self
.clk_sel_i
= Signal(2, reset_less
=True)
1579 self
.ref_clk
= ClockSignal() # can't rename it but that's ok
1580 self
.pllclk_clk
= ClockSignal("pllclk")
1582 def elaborate(self
, platform
):
1586 # TestIssuer nominally runs at main clock, actually it is
1587 # all combinatorial internally except for coresync'd components
1588 m
.submodules
.ti
= ti
= self
.ti
1591 # ClockSelect runs at PLL output internal clock rate
1592 m
.submodules
.wrappll
= pll
= self
.pll
1594 # add clock domains from PLL
1595 cd_pll
= ClockDomain("pllclk")
1598 # PLL clock established. has the side-effect of running clklsel
1599 # at the PLL's speed (see DomainRenamer("pllclk") above)
1600 pllclk
= self
.pllclk_clk
1601 comb
+= pllclk
.eq(pll
.clk_pll_o
)
1603 # wire up external 24mhz to PLL
1604 #comb += pll.clk_24_i.eq(self.ref_clk)
1605 # output 18 mhz PLL test signal, and analog oscillator out
1606 comb
+= self
.pll_test_o
.eq(pll
.pll_test_o
)
1607 comb
+= self
.pll_vco_o
.eq(pll
.pll_vco_o
)
1609 # input to pll clock selection
1610 comb
+= pll
.clk_sel_i
.eq(self
.clk_sel_i
)
1612 # now wire up ResetSignals. don't mind them being in this domain
1613 pll_rst
= ResetSignal("pllclk")
1614 comb
+= pll_rst
.eq(ResetSignal())
1616 # internal clock is set to selector clock-out. has the side-effect of
1617 # running TestIssuer at this speed (see DomainRenamer("intclk") above)
1618 # debug clock runs at coresync internal clock
1619 if self
.ti
.dbg_domain
!= 'sync':
1620 cd_dbgsync
= ClockDomain("dbgsync")
1621 intclk
= ClockSignal(self
.ti
.core_domain
)
1622 dbgclk
= ClockSignal(self
.ti
.dbg_domain
)
1623 # XXX BYPASS PLL XXX
1624 # XXX BYPASS PLL XXX
1625 # XXX BYPASS PLL XXX
1627 comb
+= intclk
.eq(self
.ref_clk
)
1628 assert self
.ti
.core_domain
!= 'sync', \
1629 "cannot set core_domain to sync and use pll at the same time"
1631 if self
.ti
.core_domain
!= 'sync':
1632 comb
+= intclk
.eq(ClockSignal())
1633 if self
.ti
.dbg_domain
!= 'sync':
1634 dbgclk
= ClockSignal(self
.ti
.dbg_domain
)
1635 comb
+= dbgclk
.eq(intclk
)
1636 comb
+= self
.ti
.dbg_rst_i
.eq(self
.dbg_rst_i
)
1641 return list(self
.ti
.ports()) + list(self
.pll
.ports()) + \
1642 [ClockSignal(), ResetSignal()]
1644 def external_ports(self
):
1645 ports
= self
.ti
.external_ports()
1646 ports
.append(ClockSignal())
1647 ports
.append(ResetSignal())
1649 ports
.append(self
.clk_sel_i
)
1650 ports
.append(self
.pll
.clk_24_i
)
1651 ports
.append(self
.pll_test_o
)
1652 ports
.append(self
.pll_vco_o
)
1653 ports
.append(self
.pllclk_clk
)
1654 ports
.append(self
.ref_clk
)
1658 if __name__
== '__main__':
1659 units
= {'alu': 1, 'cr': 1, 'branch': 1, 'trap': 1, 'logical': 1,
1665 pspec
= TestMemPspec(ldst_ifacetype
='bare_wb',
1666 imem_ifacetype
='bare_wb',
1671 dut
= TestIssuer(pspec
)
1672 vl
= main(dut
, ports
=dut
.ports(), name
="test_issuer")
1674 if len(sys
.argv
) == 1:
1675 vl
= rtlil
.convert(dut
, ports
=dut
.external_ports(), name
="test_issuer")
1676 with
open("test_issuer.il", "w") as f
: