src/soc/simple/issuer.py

   1 """simple core issuer
   2
   3 not in any way intended for production use.  this runs a FSM that:
   4
   5 * reads the Program Counter from StateRegs
   6 * reads an instruction from a fixed-size Test Memory
   7 * issues it to the Simple Core
   8 * waits for it to complete
   9 * increments the PC
  10 * does it all over again
  11
  12 the purpose of this module is to verify the functional correctness
  13 of the Function Units in the absolute simplest and clearest possible
  14 way, and to at provide something that can be further incrementally
  15 improved.
  16 """
  17
  18 from nmigen import (Elaboratable, Module, Signal, ClockSignal, ResetSignal,
  19                     ClockDomain, DomainRenamer, Mux, Const)
  20 from nmigen.cli import rtlil
  21 from nmigen.cli import main
  22 import sys
  23
  24 from soc.decoder.power_decoder import create_pdecode
  25 from soc.decoder.power_decoder2 import PowerDecode2, SVP64PrefixDecoder
  26 from soc.decoder.decode2execute1 import IssuerDecode2ToOperand
  27 from soc.decoder.decode2execute1 import Data
  28 from soc.experiment.testmem import TestMemory # test only for instructions
  29 from soc.regfile.regfiles import StateRegs, FastRegs
  30 from soc.simple.core import NonProductionCore
  31 from soc.config.test.test_loadstore import TestMemPspec
  32 from soc.config.ifetch import ConfigFetchUnit
  33 from soc.decoder.power_enums import MicrOp
  34 from soc.debug.dmi import CoreDebug, DMIInterface
  35 from soc.debug.jtag import JTAG
  36 from soc.config.pinouts import get_pinspecs
  37 from soc.config.state import CoreState
  38 from soc.interrupts.xics import XICS_ICP, XICS_ICS
  39 from soc.bus.simple_gpio import SimpleGPIO
  40 from soc.bus.SPBlock512W64B8W import SPBlock512W64B8W
  41 from soc.clock.select import ClockSelect
  42 from soc.clock.dummypll import DummyPLL
  43 from soc.sv.svstate import SVSTATERec
  44
  45
  46 from nmutil.util import rising_edge
  47
  48 def get_insn(f_instr_o, pc):
  49     if f_instr_o.width == 32:
  50         return f_instr_o
  51     else:
  52         # 64-bit: bit 2 of pc decides which word to select
  53         return f_instr_o.word_select(pc[2], 32)
  54
  55
  56 class TestIssuerInternal(Elaboratable):
  57     """TestIssuer - reads instructions from TestMemory and issues them
  58
  59     efficiency and speed is not the main goal here: functional correctness is.
  60     """
  61     def __init__(self, pspec):
  62
  63         # JTAG interface.  add this right at the start because if it's
  64         # added it *modifies* the pspec, by adding enable/disable signals
  65         # for parts of the rest of the core
  66         self.jtag_en = hasattr(pspec, "debug") and pspec.debug == 'jtag'
  67         if self.jtag_en:
  68             subset = {'uart', 'mtwi', 'eint', 'gpio', 'mspi0', 'mspi1',
  69                       'pwm', 'sd0', 'sdr'}
  70             self.jtag = JTAG(get_pinspecs(subset=subset))
  71             # add signals to pspec to enable/disable icache and dcache
  72             # (or data and intstruction wishbone if icache/dcache not included)
  73             # https://bugs.libre-soc.org/show_bug.cgi?id=520
  74             # TODO: do we actually care if these are not domain-synchronised?
  75             # honestly probably not.
  76             pspec.wb_icache_en = self.jtag.wb_icache_en
  77             pspec.wb_dcache_en = self.jtag.wb_dcache_en
  78             self.wb_sram_en = self.jtag.wb_sram_en
  79         else:
  80             self.wb_sram_en = Const(1)
  81
  82         # add 4k sram blocks?
  83         self.sram4x4k = (hasattr(pspec, "sram4x4kblock") and
  84                          pspec.sram4x4kblock == True)
  85         if self.sram4x4k:
  86             self.sram4k = []
  87             for i in range(4):
  88                 self.sram4k.append(SPBlock512W64B8W(name="sram4k_%d" % i))
  89
  90         # add interrupt controller?
  91         self.xics = hasattr(pspec, "xics") and pspec.xics == True
  92         if self.xics:
  93             self.xics_icp = XICS_ICP()
  94             self.xics_ics = XICS_ICS()
  95             self.int_level_i = self.xics_ics.int_level_i
  96
  97         # add GPIO peripheral?
  98         self.gpio = hasattr(pspec, "gpio") and pspec.gpio == True
  99         if self.gpio:
 100             self.simple_gpio = SimpleGPIO()
 101             self.gpio_o = self.simple_gpio.gpio_o
 102
 103         # main instruction core25
 104         self.core = core = NonProductionCore(pspec)
 105
 106         # instruction decoder.  goes into Trap Record
 107         pdecode = create_pdecode()
 108         self.cur_state = CoreState("cur") # current state (MSR/PC/EINT/SVSTATE)
 109         self.pdecode2 = PowerDecode2(pdecode, state=self.cur_state,
 110                                      opkls=IssuerDecode2ToOperand)
 111         self.svp64 = SVP64PrefixDecoder() # for decoding SVP64 prefix
 112
 113         # Test Instruction memory
 114         self.imem = ConfigFetchUnit(pspec).fu
 115         # one-row cache of instruction read
 116         self.iline = Signal(64) # one instruction line
 117         self.iprev_adr = Signal(64) # previous address: if different, do read
 118
 119         # DMI interface
 120         self.dbg = CoreDebug()
 121
 122         # instruction go/monitor
 123         self.pc_o = Signal(64, reset_less=True)
 124         self.pc_i = Data(64, "pc_i") # set "ok" to indicate "please change me"
 125         self.core_bigendian_i = Signal()
 126         self.busy_o = Signal(reset_less=True)
 127         self.memerr_o = Signal(reset_less=True)
 128
 129         # STATE regfile read /write ports for PC, MSR, SVSTATE
 130         staterf = self.core.regs.rf['state']
 131         self.state_r_pc = staterf.r_ports['cia'] # PC rd
 132         self.state_w_pc = staterf.w_ports['d_wr1'] # PC wr
 133         self.state_r_msr = staterf.r_ports['msr'] # MSR rd
 134         self.state_r_sv = staterf.r_ports['sv'] # SVSTATE rd
 135         self.state_w_sv = staterf.w_ports['sv'] # SVSTATE wr
 136
 137         # DMI interface access
 138         intrf = self.core.regs.rf['int']
 139         crrf = self.core.regs.rf['cr']
 140         xerrf = self.core.regs.rf['xer']
 141         self.int_r = intrf.r_ports['dmi'] # INT read
 142         self.cr_r = crrf.r_ports['full_cr_dbg'] # CR read
 143         self.xer_r = xerrf.r_ports['full_xer'] # XER read
 144
 145         # hack method of keeping an eye on whether branch/trap set the PC
 146         self.state_nia = self.core.regs.rf['state'].w_ports['nia']
 147         self.state_nia.wen.name = 'state_nia_wen'
 148
 149     def fetch_fsm(self, m, core, dbg, pc, nia,
 150                         core_rst, cur_state,
 151                         fetch_pc_ready_o, fetch_pc_valid_i,
 152                         exec_insn_valid_o, exec_insn_ready_i,
 153                         fetch_insn_o):
 154         """fetch FSM
 155         this FSM performs fetch of raw instruction data, partial-decodes
 156         it 32-bit at a time to detect SVP64 prefixes, and will optionally
 157         read a 2nd 32-bit quantity if that occurs.
 158         """
 159         comb = m.d.comb
 160         sync = m.d.sync
 161         pdecode2 = self.pdecode2
 162         svp64 = self.svp64
 163
 164         msr_read = Signal(reset=1)
 165         sv_read = Signal(reset=1)
 166
 167         with m.FSM(name='fetch_fsm'):
 168
 169             # waiting (zzz)
 170             with m.State("IDLE"):
 171                 with m.If(~dbg.core_stop_o & ~core_rst):
 172                     comb += fetch_pc_ready_o.eq(1)
 173                     with m.If(fetch_pc_valid_i):
 174                         # instruction allowed to go: start by reading the PC
 175                         # capture the PC and also drop it into Insn Memory
 176                         # we have joined a pair of combinatorial memory
 177                         # lookups together.  this is Generally Bad.
 178                         comb += self.imem.a_pc_i.eq(pc)
 179                         comb += self.imem.a_valid_i.eq(1)
 180                         comb += self.imem.f_valid_i.eq(1)
 181                         sync += cur_state.pc.eq(pc)
 182
 183                         # initiate read of MSR/SVSTATE. arrives one clock later
 184                         comb += self.state_r_msr.ren.eq(1 << StateRegs.MSR)
 185                         comb += self.state_r_sv.ren.eq(1 << StateRegs.SVSTATE)
 186                         sync += msr_read.eq(0)
 187                         sync += sv_read.eq(0)
 188
 189                         m.next = "INSN_READ"  # move to "wait for bus" phase
 190                 with m.Else():
 191                     comb += core.core_stopped_i.eq(1)
 192                     comb += dbg.core_stopped_i.eq(1)
 193
 194             # dummy pause to find out why simulation is not keeping up
 195             with m.State("INSN_READ"):
 196                 # one cycle later, msr/sv read arrives.  valid only once.
 197                 with m.If(~msr_read):
 198                     sync += msr_read.eq(1) # yeah don't read it again
 199                     sync += cur_state.msr.eq(self.state_r_msr.data_o)
 200                 with m.If(~sv_read):
 201                     sync += sv_read.eq(1) # yeah don't read it again
 202                     sync += cur_state.svstate.eq(self.state_r_sv.data_o)
 203                 with m.If(self.imem.f_busy_o): # zzz...
 204                     # busy: stay in wait-read
 205                     comb += self.imem.a_valid_i.eq(1)
 206                     comb += self.imem.f_valid_i.eq(1)
 207                 with m.Else():
 208                     # not busy: instruction fetched
 209                     insn = get_insn(self.imem.f_instr_o, cur_state.pc)
 210                     # decode the SVP64 prefix, if any
 211                     comb += svp64.raw_opcode_in.eq(insn)
 212                     comb += svp64.bigendian.eq(self.core_bigendian_i)
 213                     # pass the decoded prefix (if any) to PowerDecoder2
 214                     sync += pdecode2.sv_rm.eq(svp64.svp64_rm)
 215                     # calculate the address of the following instruction
 216                     insn_size = Mux(svp64.is_svp64_mode, 8, 4)
 217                     sync += nia.eq(cur_state.pc + insn_size)
 218                     with m.If(~svp64.is_svp64_mode):
 219                         # with no prefix, store the instruction
 220                         # and hand it directly to the next FSM
 221                         sync += fetch_insn_o.eq(insn)
 222                         m.next = "INSN_READY"
 223                     with m.Else():
 224                         # fetch the rest of the instruction from memory
 225                         comb += self.imem.a_pc_i.eq(cur_state.pc + 4)
 226                         comb += self.imem.a_valid_i.eq(1)
 227                         comb += self.imem.f_valid_i.eq(1)
 228                         m.next = "INSN_READ2"
 229
 230             with m.State("INSN_READ2"):
 231                 with m.If(self.imem.f_busy_o):  # zzz...
 232                     # busy: stay in wait-read
 233                     comb += self.imem.a_valid_i.eq(1)
 234                     comb += self.imem.f_valid_i.eq(1)
 235                 with m.Else():
 236                     # not busy: instruction fetched
 237                     insn = get_insn(self.imem.f_instr_o, cur_state.pc+4)
 238                     sync += fetch_insn_o.eq(insn)
 239                     m.next = "INSN_READY"
 240
 241             with m.State("INSN_READY"):
 242                 # hand over the instruction, to be decoded
 243                 comb += exec_insn_valid_o.eq(1)
 244                 with m.If(exec_insn_ready_i):
 245                     m.next = "IDLE"
 246
 247     def execute_fsm(self, m, core, insn_done, pc_changed,
 248                         cur_state, fetch_insn_o,
 249                         fetch_pc_ready_o, fetch_pc_valid_i,
 250                         exec_insn_valid_o, exec_insn_ready_i):
 251         """execute FSM
 252
 253         decode / issue / execute FSM.  this interacts with the "fetch" FSM
 254         through fetch_pc_ready/valid (incoming) and exec_insn_ready/valid
 255         (outgoing).  SVP64 RM prefixes have already been set up by the
 256         "fetch" phase, so execute is fairly straightforward.
 257         """
 258
 259         comb = m.d.comb
 260         sync = m.d.sync
 261         pdecode2 = self.pdecode2
 262         svp64 = self.svp64
 263
 264         # temporaries
 265         dec_opcode_i = pdecode2.dec.raw_opcode_in # raw opcode
 266         core_busy_o = core.busy_o                 # core is busy
 267         core_ivalid_i = core.ivalid_i             # instruction is valid
 268         core_issue_i = core.issue_i               # instruction is issued
 269         insn_type = core.e.do.insn_type           # instruction MicroOp type
 270
 271         with m.FSM():
 272
 273             # go fetch the instruction at the current PC
 274             # at this point, there is no instruction running, that
 275             # could inadvertently update the PC.
 276             with m.State("INSN_FETCH"):
 277                 comb += fetch_pc_valid_i.eq(1)
 278                 with m.If(fetch_pc_ready_o):
 279                     m.next = "INSN_WAIT"
 280
 281             # decode the instruction when it arrives
 282             with m.State("INSN_WAIT"):
 283                 comb += exec_insn_ready_i.eq(1)
 284                 with m.If(exec_insn_valid_o):
 285                     # decode the instruction
 286                     comb += dec_opcode_i.eq(fetch_insn_o)  # actual opcode
 287                     sync += core.e.eq(pdecode2.e)
 288                     sync += core.state.eq(cur_state)
 289                     sync += core.raw_insn_i.eq(dec_opcode_i)
 290                     sync += core.bigendian_i.eq(self.core_bigendian_i)
 291                     # also drop PC and MSR into decode "state"
 292                     m.next = "INSN_START" # move to "start"
 293
 294             # waiting for instruction bus (stays there until not busy)
 295             with m.State("INSN_START"):
 296                 comb += core_ivalid_i.eq(1) # instruction is valid
 297                 comb += core_issue_i.eq(1)  # and issued
 298
 299                 m.next = "INSN_ACTIVE" # move to "wait completion"
 300
 301             # instruction started: must wait till it finishes
 302             with m.State("INSN_ACTIVE"):
 303                 with m.If(insn_type != MicrOp.OP_NOP):
 304                     comb += core_ivalid_i.eq(1) # instruction is valid
 305                 with m.If(self.state_nia.wen & (1<<StateRegs.PC)):
 306                     sync += pc_changed.eq(1)
 307                 with m.If(~core_busy_o): # instruction done!
 308                     comb += insn_done.eq(1)
 309                     sync += core.e.eq(0)
 310                     sync += core.raw_insn_i.eq(0)
 311                     sync += core.bigendian_i.eq(0)
 312                     sync += pc_changed.eq(0)
 313                     m.next = "INSN_FETCH"  # back to fetch
 314
 315     def elaborate(self, platform):
 316         m = Module()
 317         comb, sync = m.d.comb, m.d.sync
 318
 319         m.submodules.core = core = DomainRenamer("coresync")(self.core)
 320         m.submodules.imem = imem = self.imem
 321         m.submodules.dbg = dbg = self.dbg
 322         if self.jtag_en:
 323             m.submodules.jtag = jtag = self.jtag
 324             # TODO: UART2GDB mux, here, from external pin
 325             # see https://bugs.libre-soc.org/show_bug.cgi?id=499
 326             sync += dbg.dmi.connect_to(jtag.dmi)
 327
 328         cur_state = self.cur_state
 329
 330         # 4x 4k SRAM blocks.  these simply "exist", they get routed in litex
 331         if self.sram4x4k:
 332             for i, sram in enumerate(self.sram4k):
 333                 m.submodules["sram4k_%d" % i] = sram
 334                 comb += sram.enable.eq(self.wb_sram_en)
 335
 336         # XICS interrupt handler
 337         if self.xics:
 338             m.submodules.xics_icp = icp = self.xics_icp
 339             m.submodules.xics_ics = ics = self.xics_ics
 340             comb += icp.ics_i.eq(ics.icp_o)           # connect ICS to ICP
 341             sync += cur_state.eint.eq(icp.core_irq_o) # connect ICP to core
 342
 343         # GPIO test peripheral
 344         if self.gpio:
 345             m.submodules.simple_gpio = simple_gpio = self.simple_gpio
 346
 347         # connect one GPIO output to ICS bit 15 (like in microwatt soc.vhdl)
 348         # XXX causes litex ECP5 test to get wrong idea about input and output
 349         # (but works with verilator sim *sigh*)
 350         #if self.gpio and self.xics:
 351         #   comb += self.int_level_i[15].eq(simple_gpio.gpio_o[0])
 352
 353         # instruction decoder
 354         pdecode = create_pdecode()
 355         m.submodules.dec2 = pdecode2 = self.pdecode2
 356         m.submodules.svp64 = svp64 = self.svp64
 357
 358         # convenience
 359         dmi, d_reg, d_cr, d_xer, = dbg.dmi, dbg.d_gpr, dbg.d_cr, dbg.d_xer
 360         intrf = self.core.regs.rf['int']
 361
 362         # clock delay power-on reset
 363         cd_por  = ClockDomain(reset_less=True)
 364         cd_sync = ClockDomain()
 365         core_sync = ClockDomain("coresync")
 366         m.domains += cd_por, cd_sync, core_sync
 367
 368         ti_rst = Signal(reset_less=True)
 369         delay = Signal(range(4), reset=3)
 370         with m.If(delay != 0):
 371             m.d.por += delay.eq(delay - 1)
 372         comb += cd_por.clk.eq(ClockSignal())
 373
 374         # power-on reset delay
 375         core_rst = ResetSignal("coresync")
 376         comb += ti_rst.eq(delay != 0 | dbg.core_rst_o | ResetSignal())
 377         comb += core_rst.eq(ti_rst)
 378
 379         # busy/halted signals from core
 380         comb += self.busy_o.eq(core.busy_o)
 381         comb += pdecode2.dec.bigendian.eq(self.core_bigendian_i)
 382
 383         # temporary hack: says "go" immediately for both address gen and ST
 384         l0 = core.l0
 385         ldst = core.fus.fus['ldst0']
 386         st_go_edge = rising_edge(m, ldst.st.rel_o)
 387         m.d.comb += ldst.ad.go_i.eq(ldst.ad.rel_o) # link addr-go direct to rel
 388         m.d.comb += ldst.st.go_i.eq(st_go_edge) # link store-go to rising rel
 389
 390         # PC and instruction from I-Memory
 391         comb += self.pc_o.eq(cur_state.pc)
 392
 393         # address of the next instruction, in the absence of a branch
 394         # depends on the instruction size
 395         nia = Signal(64, reset_less=True)
 396
 397         # read the PC
 398         pc = Signal(64, reset_less=True)
 399         pc_ok_delay = Signal()
 400         sync += pc_ok_delay.eq(~self.pc_i.ok)
 401         with m.If(self.pc_i.ok):
 402             # incoming override (start from pc_i)
 403             comb += pc.eq(self.pc_i.data)
 404         with m.Else():
 405             # otherwise read StateRegs regfile for PC...
 406             comb += self.state_r_pc.ren.eq(1<<StateRegs.PC)
 407         # ... but on a 1-clock delay
 408         with m.If(pc_ok_delay):
 409             comb += pc.eq(self.state_r_pc.data_o)
 410
 411         # don't write pc every cycle
 412         comb += self.state_w_pc.wen.eq(0)
 413         comb += self.state_w_pc.data_i.eq(0)
 414
 415         # don't read msr or svstate every cycle
 416         comb += self.state_r_sv.ren.eq(0)
 417         comb += self.state_r_msr.ren.eq(0)
 418
 419         # connect up debug signals
 420         # TODO comb += core.icache_rst_i.eq(dbg.icache_rst_o)
 421         comb += dbg.terminate_i.eq(core.core_terminate_o)
 422         comb += dbg.state.pc.eq(pc)
 423         #comb += dbg.state.pc.eq(cur_state.pc)
 424         comb += dbg.state.msr.eq(cur_state.msr)
 425
 426         # there are *TWO* FSMs, one fetch (32/64-bit) one decode/execute.
 427         # these are the handshake signals between fetch and decode/execute
 428
 429         # fetch FSM can run as soon as the PC is valid
 430         fetch_pc_valid_i = Signal() # Execute tells Fetch "start next read"
 431         fetch_pc_ready_o = Signal() # Fetch Tells SVSTATE "proceed"
 432
 433         # SVSTATE FSM TODO. actually, an "Issue" FSM that happens to do SVSTATE
 434         fetch_to_sv_ready_i = Signal()
 435         fetch_to_sv_valid_o = Signal()
 436
 437         sv_to_exec_ready_i = Signal()
 438         sv_to_exec_valid_o = Signal()
 439
 440         # when done, deliver the instruction to the next FSM
 441         exec_insn_valid_o = Signal()
 442         exec_insn_ready_i = Signal() # Execute acknowledges SVSTATE
 443
 444         # latches copy of raw fetched instruction
 445         fetch_insn_o = Signal(32, reset_less=True)
 446
 447         # actually use a nmigen FSM for the first time (w00t)
 448         # this FSM is perhaps unusual in that it detects conditions
 449         # then "holds" information, combinatorially, for the core
 450         # (as opposed to using sync - which would be on a clock's delay)
 451         # this includes the actual opcode, valid flags and so on.
 452
 453         self.fetch_fsm(m, core, dbg, pc, nia,
 454                        core_rst, cur_state,
 455                        fetch_pc_ready_o, fetch_pc_valid_i,
 456                        exec_insn_valid_o, exec_insn_ready_i,
 457                        fetch_insn_o)
 458
 459         # TODO: an SVSTATE-based for-loop FSM that goes in between
 460         # fetch pc/insn ready/valid and advances SVSTATE.srcstep
 461         # until it reaches VL-1 or PowerDecoder2.no_out_vec is True.
 462
 463         # code-morph: moving the actual PC-setting out of "execute"
 464         # so that it's easier to move this into an "issue" FSM.
 465
 466         # ok here we are not reading the branch unit.  TODO
 467         # this just blithely overwrites whatever pipeline
 468         # updated the PC
 469         pc_changed = Signal() # note write to PC
 470         insn_done = Signal()  # fires just once
 471         core_busy_o = core.busy_o                 # core is busy
 472         with m.If(insn_done & (~pc_changed) & (~core_busy_o)):
 473             comb += self.state_w_pc.wen.eq(1<<StateRegs.PC)
 474             comb += self.state_w_pc.data_i.eq(nia)
 475
 476         self.execute_fsm(m, core, insn_done, pc_changed,
 477                         cur_state, fetch_insn_o,
 478                         fetch_pc_ready_o, fetch_pc_valid_i,
 479                         exec_insn_valid_o, exec_insn_ready_i)
 480
 481         # for updating svstate (things like srcstep etc.)
 482         update_svstate = Signal() # TODO: move this somewhere above
 483         new_svstate = SVSTATERec("new_svstate") # and move this as well
 484         # check if svstate needs updating: if so, write it to State Regfile
 485         with m.If(update_svstate):
 486             comb += self.state_w_sv.wen.eq(1<<StateRegs.SVSTATE)
 487             comb += self.state_w_sv.data_i.eq(new_svstate)
 488
 489         # this bit doesn't have to be in the FSM: connect up to read
 490         # regfiles on demand from DMI
 491         with m.If(d_reg.req): # request for regfile access being made
 492             # TODO: error-check this
 493             # XXX should this be combinatorial?  sync better?
 494             if intrf.unary:
 495                 comb += self.int_r.ren.eq(1<<d_reg.addr)
 496             else:
 497                 comb += self.int_r.addr.eq(d_reg.addr)
 498                 comb += self.int_r.ren.eq(1)
 499         d_reg_delay  = Signal()
 500         sync += d_reg_delay.eq(d_reg.req)
 501         with m.If(d_reg_delay):
 502             # data arrives one clock later
 503             comb += d_reg.data.eq(self.int_r.data_o)
 504             comb += d_reg.ack.eq(1)
 505
 506         # sigh same thing for CR debug
 507         with m.If(d_cr.req): # request for regfile access being made
 508             comb += self.cr_r.ren.eq(0b11111111) # enable all
 509         d_cr_delay  = Signal()
 510         sync += d_cr_delay.eq(d_cr.req)
 511         with m.If(d_cr_delay):
 512             # data arrives one clock later
 513             comb += d_cr.data.eq(self.cr_r.data_o)
 514             comb += d_cr.ack.eq(1)
 515
 516         # aaand XER...
 517         with m.If(d_xer.req): # request for regfile access being made
 518             comb += self.xer_r.ren.eq(0b111111) # enable all
 519         d_xer_delay  = Signal()
 520         sync += d_xer_delay.eq(d_xer.req)
 521         with m.If(d_xer_delay):
 522             # data arrives one clock later
 523             comb += d_xer.data.eq(self.xer_r.data_o)
 524             comb += d_xer.ack.eq(1)
 525
 526         # DEC and TB inc/dec FSM.  copy of DEC is put into CoreState,
 527         # (which uses that in PowerDecoder2 to raise 0x900 exception)
 528         self.tb_dec_fsm(m, cur_state.dec)
 529
 530         return m
 531
 532     def tb_dec_fsm(self, m, spr_dec):
 533         """tb_dec_fsm
 534
 535         this is a FSM for updating either dec or tb.  it runs alternately
 536         DEC, TB, DEC, TB.  note that SPR pipeline could have written a new
 537         value to DEC, however the regfile has "passthrough" on it so this
 538         *should* be ok.
 539
 540         see v3.0B p1097-1099 for Timeer Resource and p1065 and p1076
 541         """
 542
 543         comb, sync = m.d.comb, m.d.sync
 544         fast_rf = self.core.regs.rf['fast']
 545         fast_r_dectb = fast_rf.r_ports['issue'] # DEC/TB
 546         fast_w_dectb = fast_rf.w_ports['issue'] # DEC/TB
 547
 548         with m.FSM() as fsm:
 549
 550             # initiates read of current DEC
 551             with m.State("DEC_READ"):
 552                 comb += fast_r_dectb.addr.eq(FastRegs.DEC)
 553                 comb += fast_r_dectb.ren.eq(1)
 554                 m.next = "DEC_WRITE"
 555
 556             # waits for DEC read to arrive (1 cycle), updates with new value
 557             with m.State("DEC_WRITE"):
 558                 new_dec = Signal(64)
 559                 # TODO: MSR.LPCR 32-bit decrement mode
 560                 comb += new_dec.eq(fast_r_dectb.data_o - 1)
 561                 comb += fast_w_dectb.addr.eq(FastRegs.DEC)
 562                 comb += fast_w_dectb.wen.eq(1)
 563                 comb += fast_w_dectb.data_i.eq(new_dec)
 564                 sync += spr_dec.eq(new_dec) # copy into cur_state for decoder
 565                 m.next = "TB_READ"
 566
 567             # initiates read of current TB
 568             with m.State("TB_READ"):
 569                 comb += fast_r_dectb.addr.eq(FastRegs.TB)
 570                 comb += fast_r_dectb.ren.eq(1)
 571                 m.next = "TB_WRITE"
 572
 573             # waits for read TB to arrive, initiates write of current TB
 574             with m.State("TB_WRITE"):
 575                 new_tb = Signal(64)
 576                 comb += new_tb.eq(fast_r_dectb.data_o + 1)
 577                 comb += fast_w_dectb.addr.eq(FastRegs.TB)
 578                 comb += fast_w_dectb.wen.eq(1)
 579                 comb += fast_w_dectb.data_i.eq(new_tb)
 580                 m.next = "DEC_READ"
 581
 582         return m
 583
 584     def __iter__(self):
 585         yield from self.pc_i.ports()
 586         yield self.pc_o
 587         yield self.memerr_o
 588         yield from self.core.ports()
 589         yield from self.imem.ports()
 590         yield self.core_bigendian_i
 591         yield self.busy_o
 592
 593     def ports(self):
 594         return list(self)
 595
 596     def external_ports(self):
 597         ports = self.pc_i.ports()
 598         ports += [self.pc_o, self.memerr_o, self.core_bigendian_i, self.busy_o,
 599                 ]
 600
 601         if self.jtag_en:
 602             ports += list(self.jtag.external_ports())
 603         else:
 604             # don't add DMI if JTAG is enabled
 605             ports += list(self.dbg.dmi.ports())
 606
 607         ports += list(self.imem.ibus.fields.values())
 608         ports += list(self.core.l0.cmpi.lsmem.lsi.slavebus.fields.values())
 609
 610         if self.sram4x4k:
 611             for sram in self.sram4k:
 612                 ports += list(sram.bus.fields.values())
 613
 614         if self.xics:
 615             ports += list(self.xics_icp.bus.fields.values())
 616             ports += list(self.xics_ics.bus.fields.values())
 617             ports.append(self.int_level_i)
 618
 619         if self.gpio:
 620             ports += list(self.simple_gpio.bus.fields.values())
 621             ports.append(self.gpio_o)
 622
 623         return ports
 624
 625     def ports(self):
 626         return list(self)
 627
 628
 629 class TestIssuer(Elaboratable):
 630     def __init__(self, pspec):
 631         self.ti = TestIssuerInternal(pspec)
 632
 633         self.pll = DummyPLL()
 634
 635         # PLL direct clock or not
 636         self.pll_en = hasattr(pspec, "use_pll") and pspec.use_pll
 637         if self.pll_en:
 638             self.pll_18_o = Signal(reset_less=True)
 639
 640     def elaborate(self, platform):
 641         m = Module()
 642         comb = m.d.comb
 643
 644         # TestIssuer runs at direct clock
 645         m.submodules.ti = ti = self.ti
 646         cd_int = ClockDomain("coresync")
 647
 648         if self.pll_en:
 649             # ClockSelect runs at PLL output internal clock rate
 650             m.submodules.pll = pll = self.pll
 651
 652             # add clock domains from PLL
 653             cd_pll = ClockDomain("pllclk")
 654             m.domains += cd_pll
 655
 656             # PLL clock established.  has the side-effect of running clklsel
 657             # at the PLL's speed (see DomainRenamer("pllclk") above)
 658             pllclk = ClockSignal("pllclk")
 659             comb += pllclk.eq(pll.clk_pll_o)
 660
 661             # wire up external 24mhz to PLL
 662             comb += pll.clk_24_i.eq(ClockSignal())
 663
 664             # output 18 mhz PLL test signal
 665             comb += self.pll_18_o.eq(pll.pll_18_o)
 666
 667             # now wire up ResetSignals.  don't mind them being in this domain
 668             pll_rst = ResetSignal("pllclk")
 669             comb += pll_rst.eq(ResetSignal())
 670
 671         # internal clock is set to selector clock-out.  has the side-effect of
 672         # running TestIssuer at this speed (see DomainRenamer("intclk") above)
 673         intclk = ClockSignal("coresync")
 674         if self.pll_en:
 675             comb += intclk.eq(pll.clk_pll_o)
 676         else:
 677             comb += intclk.eq(ClockSignal())
 678
 679         return m
 680
 681     def ports(self):
 682         return list(self.ti.ports()) + list(self.pll.ports()) + \
 683                [ClockSignal(), ResetSignal()]
 684
 685     def external_ports(self):
 686         ports = self.ti.external_ports()
 687         ports.append(ClockSignal())
 688         ports.append(ResetSignal())
 689         if self.pll_en:
 690             ports.append(self.pll.clk_sel_i)
 691             ports.append(self.pll_18_o)
 692             ports.append(self.pll.pll_lck_o)
 693         return ports
 694
 695
 696 if __name__ == '__main__':
 697     units = {'alu': 1, 'cr': 1, 'branch': 1, 'trap': 1, 'logical': 1,
 698              'spr': 1,
 699              'div': 1,
 700              'mul': 1,
 701              'shiftrot': 1
 702             }
 703     pspec = TestMemPspec(ldst_ifacetype='bare_wb',
 704                          imem_ifacetype='bare_wb',
 705                          addr_wid=48,
 706                          mask_wid=8,
 707                          reg_wid=64,
 708                          units=units)
 709     dut = TestIssuer(pspec)
 710     vl = main(dut, ports=dut.ports(), name="test_issuer")
 711
 712     if len(sys.argv) == 1:
 713         vl = rtlil.convert(dut, ports=dut.external_ports(), name="test_issuer")
 714         with open("test_issuer.il", "w") as f:
 715             f.write(vl)