6e2ab94c8f100baed038fd39bfedc6779aac0daa
5 * https://bugs.libre-soc.org/show_bug.cgi?id=363
7 from nmigen
import Module
, Signal
, Cat
8 from nmigen
.back
.pysim
import Simulator
, Delay
, Settle
9 from nmutil
.formaltest
import FHDLTestCase
10 from nmigen
.cli
import rtlil
12 from soc
.decoder
.isa
.caller
import special_sprs
13 from soc
.decoder
.power_decoder
import create_pdecode
14 from soc
.decoder
.power_decoder2
import PowerDecode2
15 from soc
.decoder
.isa
.all
import ISA
16 from soc
.decoder
.power_enums
import Function
, XER_bits
17 from soc
.config
.test
.test_loadstore
import TestMemPspec
19 from soc
.simple
.core
import NonProductionCore
20 from soc
.experiment
.compalu_multi
import find_ok
# hack
22 from soc
.fu
.compunits
.test
.test_compunit
import (setup_test_memory
,
25 # test with ALU data and Logical data
26 from soc
.fu
.alu
.test
.test_pipe_caller
import ALUTestCase
27 from soc
.fu
.logical
.test
.test_pipe_caller
import LogicalTestCase
28 from soc
.fu
.shift_rot
.test
.test_pipe_caller
import ShiftRotTestCase
29 from soc
.fu
.cr
.test
.test_pipe_caller
import CRTestCase
30 from soc
.fu
.branch
.test
.test_pipe_caller
import BranchTestCase
31 from soc
.fu
.ldst
.test
.test_pipe_caller
import LDSTTestCase
34 def setup_regs(core
, test
):
36 # set up INT regfile, "direct" write (bypass rd/write ports)
37 intregs
= core
.regs
.int
39 yield intregs
.regs
[i
].reg
.eq(test
.regs
[i
])
41 # set up CR regfile, "direct" write across all CRs
44 #cr = int('{:32b}'.format(cr)[::-1], 2)
45 print ("cr reg", hex(cr
))
48 cri
= (cr
>>(i
*4)) & 0xf
49 #cri = int('{:04b}'.format(cri)[::-1], 2)
50 print ("cr reg", hex(cri
), i
,
51 crregs
.regs
[i
].reg
.shape())
52 yield crregs
.regs
[i
].reg
.eq(cri
)
54 # set up XER. "direct" write (bypass rd/write ports)
56 print ("sprs", test
.sprs
)
57 if special_sprs
['XER'] in test
.sprs
:
58 xer
= test
.sprs
[special_sprs
['XER']]
59 sobit
= xer
[XER_bits
['SO']].value
60 yield xregs
.regs
[xregs
.SO
].reg
.eq(sobit
)
61 cabit
= xer
[XER_bits
['CA']].value
62 ca32bit
= xer
[XER_bits
['CA32']].value
63 yield xregs
.regs
[xregs
.CA
].reg
.eq(Cat(cabit
, ca32bit
))
64 ovbit
= xer
[XER_bits
['OV']].value
65 ov32bit
= xer
[XER_bits
['OV32']].value
66 yield xregs
.regs
[xregs
.OV
].reg
.eq(Cat(ovbit
, ov32bit
))
68 yield xregs
.regs
[xregs
.SO
].reg
.eq(0)
69 yield xregs
.regs
[xregs
.OV
].reg
.eq(0)
70 yield xregs
.regs
[xregs
.CA
].reg
.eq(0)
73 pdecode2
= core
.pdecode2
74 so
= yield xregs
.regs
[xregs
.SO
].reg
75 ov
= yield xregs
.regs
[xregs
.OV
].reg
76 ca
= yield xregs
.regs
[xregs
.CA
].reg
77 oe
= yield pdecode2
.e
.do
.oe
.oe
78 oe_ok
= yield pdecode2
.e
.do
.oe
.oe_ok
80 print ("before: so/ov-32/ca-32", so
, bin(ov
), bin(ca
))
81 print ("oe:", oe
, oe_ok
)
84 def check_regs(dut
, sim
, core
, test
, code
):
88 rval
= yield core
.regs
.int.regs
[i
].reg
90 print ("int regs", list(map(hex, intregs
)))
92 simregval
= sim
.gpr
[i
].asint()
93 dut
.assertEqual(simregval
, intregs
[i
],
94 "int reg %d not equal %s" % (i
, repr(code
)))
99 rval
= yield core
.regs
.cr
.regs
[i
].reg
101 print ("cr regs", list(map(hex, crregs
)))
104 cri
= sim
.crl
[7-i
].get_range().value
105 print ("cr reg", i
, hex(cri
), i
, hex(rval
))
106 # XXX https://bugs.libre-soc.org/show_bug.cgi?id=363
107 dut
.assertEqual(cri
, rval
,
108 "cr reg %d not equal %s" % (i
, repr(code
)))
111 xregs
= core
.regs
.xer
112 so
= yield xregs
.regs
[xregs
.SO
].reg
113 ov
= yield xregs
.regs
[xregs
.OV
].reg
114 ca
= yield xregs
.regs
[xregs
.CA
].reg
116 print ("sim SO", sim
.spr
['XER'][XER_bits
['SO']])
117 e_so
= sim
.spr
['XER'][XER_bits
['SO']].value
118 e_ov
= sim
.spr
['XER'][XER_bits
['OV']].value
119 e_ov32
= sim
.spr
['XER'][XER_bits
['OV32']].value
120 e_ca
= sim
.spr
['XER'][XER_bits
['CA']].value
121 e_ca32
= sim
.spr
['XER'][XER_bits
['CA32']].value
123 e_ov
= e_ov |
(e_ov32
<<1)
124 e_ca
= e_ca |
(e_ca32
<<1)
126 print ("after: so/ov-32/ca-32", so
, bin(ov
), bin(ca
))
127 dut
.assertEqual(e_so
, so
, "so mismatch %s" % (repr(code
)))
128 dut
.assertEqual(e_ov
, ov
, "ov mismatch %s" % (repr(code
)))
129 dut
.assertEqual(e_ca
, ca
, "ca mismatch %s" % (repr(code
)))
132 def wait_for_busy_hi(cu
):
134 busy_o
= yield cu
.busy_o
135 terminated_o
= yield cu
.core_terminated_o
136 if busy_o
or terminated_o
:
137 print("busy/terminated:", busy_o
, terminated_o
)
142 def set_issue(core
, dec2
, sim
):
143 yield core
.issue_i
.eq(1)
145 yield core
.issue_i
.eq(0)
146 yield from wait_for_busy_hi(core
)
149 def wait_for_busy_clear(cu
):
151 busy_o
= yield cu
.busy_o
158 class TestRunner(FHDLTestCase
):
159 def __init__(self
, tst_data
):
160 super().__init
__("run_all")
161 self
.test_data
= tst_data
166 instruction
= Signal(32)
169 pspec
= TestMemPspec(ldst_ifacetype
='testpi',
175 m
.submodules
.core
= core
= NonProductionCore(pspec
)
176 pdecode2
= core
.pdecode2
179 comb
+= core
.raw_opcode_i
.eq(instruction
)
180 comb
+= core
.ivalid_i
.eq(ivalid_i
)
182 # temporary hack: says "go" immediately for both address gen and ST
183 ldst
= core
.fus
.fus
['ldst0']
184 m
.d
.comb
+= ldst
.ad
.go
.eq(ldst
.ad
.rel
) # link addr-go direct to rel
185 m
.d
.comb
+= ldst
.st
.go
.eq(ldst
.st
.rel
) # link store-go direct to rel
192 yield core
.issue_i
.eq(0)
195 for test
in self
.test_data
:
197 program
= test
.program
198 self
.subTest(test
.name
)
199 sim
= ISA(pdecode2
, test
.regs
, test
.sprs
, test
.cr
, test
.mem
,
201 gen
= program
.generate_instructions()
202 instructions
= list(zip(gen
, program
.assembly
.splitlines()))
204 yield from setup_test_memory(l0
, sim
)
205 yield from setup_regs(core
, test
)
207 index
= sim
.pc
.CIA
.value
//4
208 while index
< len(instructions
):
209 ins
, code
= instructions
[index
]
211 print("instruction: 0x{:X}".format(ins
& 0xffffffff))
214 # ask the decoder to decode this binary data (endian'd)
215 yield core
.bigendian_i
.eq(0) # little / big?
216 yield instruction
.eq(ins
) # raw binary instr.
219 #fn_unit = yield pdecode2.e.fn_unit
220 #fuval = self.funit.value
221 #self.assertEqual(fn_unit & fuval, fuval)
223 # set operand and get inputs
224 yield from set_issue(core
, pdecode2
, sim
)
227 yield from wait_for_busy_clear(core
)
232 # call simulated operation
233 opname
= code
.split(' ')[0]
234 yield from sim
.call(opname
)
235 index
= sim
.pc
.CIA
.value
//4
238 yield from check_regs(self
, sim
, core
, test
, code
)
241 yield from check_sim_memory(self
, l0
, sim
, code
)
243 sim
.add_sync_process(process
)
244 with sim
.write_vcd("core_simulator.vcd", "core_simulator.gtkw",
249 if __name__
== "__main__":
250 unittest
.main(exit
=False)
251 suite
= unittest
.TestSuite()
252 suite
.addTest(TestRunner(LDSTTestCase
.test_data
))
253 suite
.addTest(TestRunner(CRTestCase
.test_data
))
254 suite
.addTest(TestRunner(ShiftRotTestCase
.test_data
))
255 suite
.addTest(TestRunner(LogicalTestCase
.test_data
))
256 suite
.addTest(TestRunner(ALUTestCase
.test_data
))
257 suite
.addTest(TestRunner(BranchTestCase
.test_data
))
259 runner
= unittest
.TextTestRunner()