src/soc/simple/test/test_core.py

   1 """simple core test
   2
   3 related bugs:
   4
   5  * https://bugs.libre-soc.org/show_bug.cgi?id=363
   6 """
   7 from nmigen import Module, Signal, Cat
   8 from nmigen.back.pysim import Simulator, Delay, Settle
   9 from nmutil.formaltest import FHDLTestCase
  10 from nmigen.cli import rtlil
  11 import unittest
  12 from soc.decoder.isa.caller import special_sprs
  13 from soc.decoder.power_decoder import create_pdecode
  14 from soc.decoder.power_decoder2 import PowerDecode2
  15 from soc.decoder.selectable_int import SelectableInt
  16 from soc.decoder.isa.all import ISA
  17 from soc.decoder.power_enums import SPR, Function, XER_bits
  18 from soc.config.test.test_loadstore import TestMemPspec
  19
  20 from soc.simple.core import NonProductionCore
  21 from soc.experiment.compalu_multi import find_ok # hack
  22
  23 from soc.fu.compunits.test.test_compunit import (setup_test_memory,
  24                                                  check_sim_memory)
  25
  26 # test with ALU data and Logical data
  27 from soc.fu.alu.test.test_pipe_caller import ALUTestCase
  28 from soc.fu.logical.test.test_pipe_caller import LogicalTestCase
  29 from soc.fu.shift_rot.test.test_pipe_caller import ShiftRotTestCase
  30 from soc.fu.cr.test.test_pipe_caller import CRTestCase
  31 from soc.fu.branch.test.test_pipe_caller import BranchTestCase
  32 from soc.fu.ldst.test.test_pipe_caller import LDSTTestCase
  33 from soc.regfile.util import spr_to_fast_reg
  34
  35
  36 def setup_regs(core, test):
  37
  38     # set up INT regfile, "direct" write (bypass rd/write ports)
  39     intregs = core.regs.int
  40     for i in range(32):
  41         yield intregs.regs[i].reg.eq(test.regs[i])
  42
  43     # set up CR regfile, "direct" write across all CRs
  44     cr = test.cr
  45     crregs = core.regs.cr
  46     #cr = int('{:32b}'.format(cr)[::-1], 2)
  47     print ("cr reg", hex(cr))
  48     for i in range(8):
  49         #j = 7-i
  50         cri = (cr>>(i*4)) & 0xf
  51         #cri = int('{:04b}'.format(cri)[::-1], 2)
  52         print ("cr reg", hex(cri), i,
  53                 crregs.regs[i].reg.shape())
  54         yield crregs.regs[i].reg.eq(cri)
  55
  56     # set up XER.  "direct" write (bypass rd/write ports)
  57     xregs = core.regs.xer
  58     print ("sprs", test.sprs)
  59     if 'XER' in test.sprs:
  60         xer = test.sprs['XER']
  61         xer = SelectableInt(xer, 64)
  62         sobit = xer[XER_bits['SO']].value
  63         yield xregs.regs[xregs.SO].reg.eq(sobit)
  64         cabit = xer[XER_bits['CA']].value
  65         ca32bit = xer[XER_bits['CA32']].value
  66         yield xregs.regs[xregs.CA].reg.eq(Cat(cabit, ca32bit))
  67         ovbit = xer[XER_bits['OV']].value
  68         ov32bit = xer[XER_bits['OV32']].value
  69         yield xregs.regs[xregs.OV].reg.eq(Cat(ovbit, ov32bit))
  70         print ("setting XER so %d ca %d ca32 %d ov %d ov32 %d" % \
  71                 (sobit, cabit, ca32bit, ovbit, ov32bit))
  72     else:
  73         yield xregs.regs[xregs.SO].reg.eq(0)
  74         yield xregs.regs[xregs.OV].reg.eq(0)
  75         yield xregs.regs[xregs.CA].reg.eq(0)
  76
  77     # setting both fast and slow SPRs from test data
  78
  79     fregs = core.regs.fast
  80     sregs = core.regs.spr
  81     for sprname, val in test.sprs.items():
  82         if sprname == 'XER':
  83             continue
  84         fast = spr_to_fast_reg(sprname)
  85         if fast is None:
  86             # match behaviour of SPRMap in power_decoder2.py
  87             for i, x in enumerate(SPR):
  88                 if sprname == x.name:
  89                     yield sregs[i].reg.eq(val)
  90                     print ("setting slow SPR %d (%s) to %x" % \
  91                             (i, sprname, val))
  92         else:
  93             yield fregs.regs[fast].reg.eq(val)
  94             print ("setting fast reg %d (%s) to %x" % \
  95                     (fast, sprname, val))
  96
  97
  98     # allow changes to settle before reporting on XER
  99     yield Settle()
 100
 101     # XER
 102     pdecode2 = core.pdecode2
 103     so = yield xregs.regs[xregs.SO].reg
 104     ov = yield xregs.regs[xregs.OV].reg
 105     ca = yield xregs.regs[xregs.CA].reg
 106     oe = yield pdecode2.e.do.oe.oe
 107     oe_ok = yield pdecode2.e.do.oe.oe_ok
 108
 109     print ("before: so/ov-32/ca-32", so, bin(ov), bin(ca))
 110     print ("oe:", oe, oe_ok)
 111
 112
 113 def check_regs(dut, sim, core, test, code):
 114     # int regs
 115     intregs = []
 116     for i in range(32):
 117         rval = yield core.regs.int.regs[i].reg
 118         intregs.append(rval)
 119     print ("int regs", list(map(hex, intregs)))
 120     for i in range(32):
 121         simregval = sim.gpr[i].asint()
 122         dut.assertEqual(simregval, intregs[i],
 123             "int reg %d not equal %s" % (i, repr(code)))
 124
 125     # CRs
 126     crregs = []
 127     for i in range(8):
 128         rval = yield core.regs.cr.regs[i].reg
 129         crregs.append(rval)
 130     print ("cr regs", list(map(hex, crregs)))
 131     for i in range(8):
 132         rval = crregs[i]
 133         cri = sim.crl[7-i].get_range().value
 134         print ("cr reg", i, hex(cri), i, hex(rval))
 135         # XXX https://bugs.libre-soc.org/show_bug.cgi?id=363
 136         dut.assertEqual(cri, rval,
 137             "cr reg %d not equal %s" % (i, repr(code)))
 138
 139     # XER
 140     xregs = core.regs.xer
 141     so = yield xregs.regs[xregs.SO].reg
 142     ov = yield xregs.regs[xregs.OV].reg
 143     ca = yield xregs.regs[xregs.CA].reg
 144
 145     print ("sim SO", sim.spr['XER'][XER_bits['SO']])
 146     e_so = sim.spr['XER'][XER_bits['SO']].value
 147     e_ov = sim.spr['XER'][XER_bits['OV']].value
 148     e_ov32 = sim.spr['XER'][XER_bits['OV32']].value
 149     e_ca = sim.spr['XER'][XER_bits['CA']].value
 150     e_ca32 = sim.spr['XER'][XER_bits['CA32']].value
 151
 152     e_ov = e_ov | (e_ov32<<1)
 153     e_ca = e_ca | (e_ca32<<1)
 154
 155     print ("after: so/ov-32/ca-32", so, bin(ov), bin(ca))
 156     dut.assertEqual(e_so, so, "so mismatch %s" % (repr(code)))
 157     dut.assertEqual(e_ov, ov, "ov mismatch %s" % (repr(code)))
 158     dut.assertEqual(e_ca, ca, "ca mismatch %s" % (repr(code)))
 159
 160
 161 def wait_for_busy_hi(cu):
 162     while True:
 163         busy_o = yield cu.busy_o
 164         terminated_o = yield cu.core_terminated_o
 165         if busy_o or terminated_o:
 166             print("busy/terminated:", busy_o, terminated_o)
 167             break
 168         print("!busy", busy_o, terminated_o)
 169         yield
 170
 171 def set_issue(core, dec2, sim):
 172     yield core.issue_i.eq(1)
 173     yield
 174     yield core.issue_i.eq(0)
 175     yield from wait_for_busy_hi(core)
 176
 177
 178 def wait_for_busy_clear(cu):
 179     while True:
 180         busy_o = yield cu.busy_o
 181         terminated_o = yield cu.core_terminated_o
 182         if not busy_o or terminated_o:
 183             print("busy/terminated:", busy_o, terminated_o)
 184             break
 185         print("busy",)
 186         yield
 187
 188
 189 class TestRunner(FHDLTestCase):
 190     def __init__(self, tst_data):
 191         super().__init__("run_all")
 192         self.test_data = tst_data
 193
 194     def run_all(self):
 195         m = Module()
 196         comb = m.d.comb
 197         instruction = Signal(32)
 198         ivalid_i = Signal()
 199
 200         pspec = TestMemPspec(ldst_ifacetype='testpi',
 201                              imem_ifacetype='',
 202                              addr_wid=48,
 203                              mask_wid=8,
 204                              reg_wid=64)
 205
 206         m.submodules.core = core = NonProductionCore(pspec)
 207         pdecode2 = core.pdecode2
 208         l0 = core.l0
 209
 210         comb += core.raw_opcode_i.eq(instruction)
 211         comb += core.ivalid_i.eq(ivalid_i)
 212
 213         # temporary hack: says "go" immediately for both address gen and ST
 214         ldst = core.fus.fus['ldst0']
 215         m.d.comb += ldst.ad.go.eq(ldst.ad.rel) # link addr-go direct to rel
 216         m.d.comb += ldst.st.go.eq(ldst.st.rel) # link store-go direct to rel
 217
 218         # nmigen Simulation
 219         sim = Simulator(m)
 220         sim.add_clock(1e-6)
 221
 222         def process():
 223             yield core.issue_i.eq(0)
 224             yield
 225
 226             for test in self.test_data:
 227                 print(test.name)
 228                 program = test.program
 229                 self.subTest(test.name)
 230                 sim = ISA(pdecode2, test.regs, test.sprs, test.cr, test.mem,
 231                           test.msr)
 232                 gen = program.generate_instructions()
 233                 instructions = list(zip(gen, program.assembly.splitlines()))
 234
 235                 yield from setup_test_memory(l0, sim)
 236                 yield from setup_regs(core, test)
 237
 238                 index = sim.pc.CIA.value//4
 239                 while index < len(instructions):
 240                     ins, code = instructions[index]
 241
 242                     print("instruction: 0x{:X}".format(ins & 0xffffffff))
 243                     print(code)
 244
 245                     # ask the decoder to decode this binary data (endian'd)
 246                     yield core.bigendian_i.eq(0)  # little / big?
 247                     yield instruction.eq(ins)          # raw binary instr.
 248                     yield ivalid_i.eq(1)
 249                     yield Settle()
 250                     #fn_unit = yield pdecode2.e.fn_unit
 251                     #fuval = self.funit.value
 252                     #self.assertEqual(fn_unit & fuval, fuval)
 253
 254                     # set operand and get inputs
 255                     yield from set_issue(core, pdecode2, sim)
 256                     yield Settle()
 257
 258                     yield from wait_for_busy_clear(core)
 259                     yield ivalid_i.eq(0)
 260                     yield
 261
 262                     print ("sim", code)
 263                     # call simulated operation
 264                     opname = code.split(' ')[0]
 265                     yield from sim.call(opname)
 266                     index = sim.pc.CIA.value//4
 267
 268                     # register check
 269                     yield from check_regs(self, sim, core, test, code)
 270
 271                     # Memory check
 272                     yield from check_sim_memory(self, l0, sim, code)
 273
 274         sim.add_sync_process(process)
 275         with sim.write_vcd("core_simulator.vcd", "core_simulator.gtkw",
 276                             traces=[]):
 277             sim.run()
 278
 279
 280 if __name__ == "__main__":
 281     unittest.main(exit=False)
 282     suite = unittest.TestSuite()
 283     suite.addTest(TestRunner(LDSTTestCase.test_data))
 284     suite.addTest(TestRunner(CRTestCase.test_data))
 285     suite.addTest(TestRunner(ShiftRotTestCase.test_data))
 286     suite.addTest(TestRunner(LogicalTestCase.test_data))
 287     suite.addTest(TestRunner(ALUTestCase.test_data))
 288     suite.addTest(TestRunner(BranchTestCase.test_data))
 289
 290     runner = unittest.TextTestRunner()
 291     runner.run(suite)
 292