4a34ff17d5fb6a4fbdd4c63f45c3a286ae6bb5d8
1 """simple core test, runs instructions from a TestMemory
5 * https://bugs.libre-soc.org/show_bug.cgi?id=363
7 from nmigen
import Module
, Signal
, Cat
8 from nmigen
.back
.pysim
import Simulator
, Delay
, Settle
9 from nmutil
.formaltest
import FHDLTestCase
10 from nmigen
.cli
import rtlil
12 from soc
.decoder
.isa
.caller
import special_sprs
13 from soc
.decoder
.isa
.all
import ISA
14 from soc
.decoder
.power_enums
import Function
, XER_bits
15 from soc
.config
.endian
import bigendian
17 from soc
.decoder
.power_decoder
import create_pdecode
18 from soc
.decoder
.power_decoder2
import PowerDecode2
20 from soc
.simple
.issuer
import TestIssuer
21 from soc
.experiment
.compalu_multi
import find_ok
# hack
23 from soc
.config
.test
.test_loadstore
import TestMemPspec
24 from soc
.simple
.test
.test_core
import (setup_regs
, check_regs
,
27 from soc
.fu
.compunits
.test
.test_compunit
import (setup_test_memory
,
29 from soc
.debug
.dmi
import DBGCore
, DBGCtrl
, DBGStat
31 # test with ALU data and Logical data
32 from soc
.fu
.alu
.test
.test_pipe_caller
import ALUTestCase
33 from soc
.fu
.div
.test
.test_pipe_caller
import DivTestCases
34 from soc
.fu
.logical
.test
.test_pipe_caller
import LogicalTestCase
35 #from soc.fu.shift_rot.test.test_pipe_caller import ShiftRotTestCase
36 from soc
.fu
.cr
.test
.test_pipe_caller
import CRTestCase
37 #from soc.fu.branch.test.test_pipe_caller import BranchTestCase
38 #from soc.fu.spr.test.test_pipe_caller import SPRTestCase
39 from soc
.fu
.ldst
.test
.test_pipe_caller
import LDSTTestCase
40 from soc
.simulator
.test_sim
import (GeneralTestCases
, AttnTestCase
)
41 #from soc.simulator.test_helloworld_sim import HelloTestCases
44 def setup_i_memory(imem
, startaddr
, instructions
):
46 print("insn before, init mem", mem
.depth
, mem
.width
, mem
,
48 for i
in range(mem
.depth
):
49 yield mem
._array
[i
].eq(0)
51 startaddr
//= 4 # instructions are 32-bit
54 for ins
in instructions
:
55 if isinstance(ins
, tuple):
59 insn
= insn
& 0xffffffff
60 yield mem
._array
[startaddr
].eq(insn
)
63 print("instr: %06x 0x%x %s" % (4*startaddr
, insn
, code
))
65 startaddr
= startaddr
& mask
70 for ins
in instructions
:
71 if isinstance(ins
, tuple):
75 insn
= insn
& 0xffffffff
76 msbs
= (startaddr
>> 1) & mask
77 val
= yield mem
._array
[msbs
]
79 print("before set", hex(4*startaddr
),
80 hex(msbs
), hex(val
), hex(insn
))
81 lsb
= 1 if (startaddr
& 1) else 0
82 val
= (val |
(insn
<< (lsb
*32)))
84 yield mem
._array
[msbs
].eq(val
)
87 print("after set", hex(4*startaddr
), hex(msbs
), hex(val
))
88 print("instr: %06x 0x%x %s %08x" % (4*startaddr
, insn
, code
, val
))
90 startaddr
= startaddr
& mask
93 def set_dmi(dmi
, addr
, data
):
95 yield dmi
.addr_i
.eq(addr
)
96 yield dmi
.din
.eq(data
)
103 yield dmi
.req_i
.eq(0)
104 yield dmi
.addr_i
.eq(0)
109 def get_dmi(dmi
, addr
):
110 yield dmi
.req_i
.eq(1)
111 yield dmi
.addr_i
.eq(addr
)
115 ack
= yield dmi
.ack_o
120 data
= yield dmi
.dout
# get data after ack valid for 1 cycle
121 yield dmi
.req_i
.eq(0)
122 yield dmi
.addr_i
.eq(0)
127 class TestRunner(FHDLTestCase
):
128 def __init__(self
, tst_data
):
129 super().__init
__("run_all")
130 self
.test_data
= tst_data
137 pspec
= TestMemPspec(ldst_ifacetype
='test_bare_wb',
138 imem_ifacetype
='test_bare_wb',
143 m
.submodules
.issuer
= issuer
= TestIssuer(pspec
)
144 imem
= issuer
.imem
._get
_memory
()
147 pdecode2
= issuer
.pdecode2
150 # copy of the decoder for simulator
151 simdec
= create_pdecode()
152 simdec2
= PowerDecode2(simdec
)
153 m
.submodules
.simdec2
= simdec2
# pain in the neck
155 comb
+= issuer
.pc_i
.data
.eq(pc_i
)
164 yield from set_dmi(dmi
, DBGCore
.CTRL
, 1<<DBGCtrl
.STOP
)
168 for test
in self
.test_data
:
171 yield from set_dmi(dmi
, DBGCore
.CTRL
, 1<<DBGCtrl
.RESET
)
173 # set up bigendian (TODO: don't do this, use MSR)
174 yield issuer
.core_bigendian_i
.eq(bigendian
)
183 program
= test
.program
184 self
.subTest(test
.name
)
185 print("regs", test
.regs
)
186 print("sprs", test
.sprs
)
188 print("mem", test
.mem
)
189 print("msr", test
.msr
)
190 print("assem", program
.assembly
)
191 gen
= list(program
.generate_instructions())
192 insncode
= program
.assembly
.splitlines()
193 instructions
= list(zip(gen
, insncode
))
194 sim
= ISA(simdec2
, test
.regs
, test
.sprs
, test
.cr
, test
.mem
,
196 initial_insns
=gen
, respect_pc
=True,
197 disassembly
=insncode
,
200 pc
= 0 # start address
201 counter
= 0 # test to pause/start
203 yield from setup_i_memory(imem
, pc
, instructions
)
204 yield from setup_test_memory(l0
, sim
)
205 yield from setup_regs(pdecode2
, core
, test
)
208 yield issuer
.pc_i
.ok
.eq(1)
211 print("instructions", instructions
)
213 index
= sim
.pc
.CIA
.value
//4
214 while index
< len(instructions
):
215 ins
, code
= instructions
[index
]
217 print("instruction: 0x{:X}".format(ins
& 0xffffffff))
223 yield from set_dmi(dmi
, DBGCore
.CTRL
, 1<<DBGCtrl
.START
)
224 yield issuer
.pc_i
.ok
.eq(0) # no change PC after this
228 counter
= counter
+ 1
230 # wait until executed
231 yield from wait_for_busy_hi(core
)
232 yield from wait_for_busy_clear(core
)
234 # set up simulated instruction (in simdec2)
236 yield from sim
.setup_one()
237 except KeyError: # indicates instruction not in imem: stop
241 # call simulated operation
243 yield from sim
.execute_one()
245 index
= sim
.pc
.CIA
.value
//4
247 terminated
= yield issuer
.dbg
.terminated_o
248 print("terminated", terminated
)
251 yield from check_regs(self
, sim
, core
, test
, code
)
254 yield from check_sim_memory(self
, l0
, sim
, code
)
256 terminated
= yield issuer
.dbg
.terminated_o
260 # test of dmi reg get
262 yield from set_dmi(dmi
, DBGCore
.GSPR_IDX
, int_reg
) # int reg 9
263 value
= yield from get_dmi(dmi
, DBGCore
.GSPR_DATA
) # get data
265 print ("after test %s reg %x value %s" % \
266 (test
.name
, int_reg
, value
))
268 sim
.add_sync_process(process
)
269 with sim
.write_vcd("issuer_simulator.vcd",
274 if __name__
== "__main__":
275 unittest
.main(exit
=False)
276 suite
= unittest
.TestSuite()
277 # suite.addTest(TestRunner(HelloTestCases.test_data))
278 suite
.addTest(TestRunner(DivTestCases().test_data
))
279 # suite.addTest(TestRunner(AttnTestCase.test_data))
280 suite
.addTest(TestRunner(GeneralTestCases
.test_data
))
281 # suite.addTest(TestRunner(LDSTTestCase().test_data))
282 # suite.addTest(TestRunner(CRTestCase().test_data))
283 # suite.addTest(TestRunner(ShiftRotTestCase.test_data))
284 suite
.addTest(TestRunner(LogicalTestCase().test_data
))
285 suite
.addTest(TestRunner(ALUTestCase().test_data
))
286 # suite.addTest(TestRunner(BranchTestCase.test_data))
287 # suite.addTest(TestRunner(SPRTestCase.test_data))
289 runner
= unittest
.TextTestRunner()