54a41b2a10069f4ff46f0fc5da2b97b02da4b771
1 """simple core test, runs instructions from a TestMemory
5 * https://bugs.libre-soc.org/show_bug.cgi?id=363
7 from nmigen
import Module
, Signal
, Cat
8 from nmigen
.back
.pysim
import Simulator
, Delay
, Settle
9 from nmutil
.formaltest
import FHDLTestCase
10 from nmigen
.cli
import rtlil
12 from soc
.decoder
.isa
.caller
import special_sprs
13 from soc
.decoder
.isa
.all
import ISA
14 from soc
.decoder
.power_enums
import Function
, XER_bits
17 from soc
.simple
.core
import TestIssuer
18 from soc
.experiment
.compalu_multi
import find_ok
# hack
20 from soc
.simple
.test
.test_core
import (setup_regs
, check_regs
,
23 from soc
.fu
.compunits
.test
.test_compunit
import (setup_test_memory
,
26 # test with ALU data and Logical data
27 from soc
.fu
.alu
.test
.test_pipe_caller
import ALUTestCase
28 from soc
.fu
.logical
.test
.test_pipe_caller
import LogicalTestCase
29 from soc
.fu
.shift_rot
.test
.test_pipe_caller
import ShiftRotTestCase
30 from soc
.fu
.cr
.test
.test_pipe_caller
import CRTestCase
31 from soc
.fu
.branch
.test
.test_pipe_caller
import BranchTestCase
32 from soc
.fu
.ldst
.test
.test_pipe_caller
import LDSTTestCase
35 def setup_i_memory(imem
, startaddr
, instructions
):
37 print ("insn before, init mem", mem
.depth
, mem
.width
, mem
)
38 for i
in range(mem
.depth
):
39 yield mem
._array
[i
].eq(0)
40 startaddr
//= 4 # assume i-mem is 32-bit wide
41 for insn
, code
in instructions
:
42 print ("instr: %06x 0x%x %s" % (4*startaddr
, insn
, code
))
43 yield mem
._array
[startaddr
].eq(insn
)
47 class TestRunner(FHDLTestCase
):
48 def __init__(self
, tst_data
):
49 super().__init
__("run_all")
50 self
.test_data
= tst_data
58 m
.submodules
.issuer
= issuer
= TestIssuer()
59 imem
= issuer
.imem
.mem
61 pdecode2
= core
.pdecode2
64 comb
+= issuer
.pc_i
.data
.eq(pc_i
)
65 comb
+= issuer
.go_insn_i
.eq(go_insn_i
)
73 for test
in self
.test_data
:
75 program
= test
.program
76 self
.subTest(test
.name
)
77 sim
= ISA(pdecode2
, test
.regs
, test
.sprs
, test
.cr
, test
.mem
,
79 gen
= program
.generate_instructions()
80 instructions
= list(zip(gen
, program
.assembly
.splitlines()))
82 pc
= 0 # start address
84 yield from setup_i_memory(imem
, pc
, instructions
)
85 yield from setup_test_memory(l0
, sim
)
86 yield from setup_regs(core
, test
)
89 yield issuer
.pc_i
.ok
.eq(1)
91 index
= sim
.pc
.CIA
.value
//4
92 while index
< len(instructions
):
93 ins
, code
= instructions
[index
]
95 print("instruction: 0x{:X}".format(ins
& 0xffffffff))
98 # start the instruction
101 yield issuer
.pc_i
.ok
.eq(0) # don't change PC from now on
102 yield go_insn_i
.eq(0) # and don't issue a new insn
104 # wait until executed
105 yield from wait_for_busy_hi(core
)
106 yield from wait_for_busy_clear(core
)
109 # call simulated operation
110 opname
= code
.split(' ')[0]
111 yield from sim
.call(opname
)
112 index
= sim
.pc
.CIA
.value
//4
115 yield from check_regs(self
, sim
, core
, test
, code
)
118 yield from check_sim_memory(self
, l0
, sim
, code
)
122 sim
.add_sync_process(process
)
123 with sim
.write_vcd("issuer_simulator.vcd",
128 if __name__
== "__main__":
129 unittest
.main(exit
=False)
130 suite
= unittest
.TestSuite()
131 #suite.addTest(TestRunner(LDSTTestCase.test_data))
132 #suite.addTest(TestRunner(CRTestCase.test_data))
133 #suite.addTest(TestRunner(ShiftRotTestCase.test_data))
134 #suite.addTest(TestRunner(LogicalTestCase.test_data))
135 suite
.addTest(TestRunner(ALUTestCase
.test_data
))
136 #suite.addTest(TestRunner(BranchTestCase.test_data))
138 runner
= unittest
.TextTestRunner()