b461c7310226c1d51bf0c131b8ad6edd8494acad
1 """simple core test, runs instructions from a TestMemory
5 * https://bugs.libre-soc.org/show_bug.cgi?id=363
7 from nmigen
import Module
, Signal
, Cat
8 from nmigen
.back
.pysim
import Simulator
, Delay
, Settle
9 from nmutil
.formaltest
import FHDLTestCase
10 from nmigen
.cli
import rtlil
12 from soc
.decoder
.isa
.caller
import special_sprs
13 from soc
.decoder
.isa
.all
import ISA
14 from soc
.decoder
.power_enums
import Function
, XER_bits
15 from soc
.config
.endian
import bigendian
17 from soc
.decoder
.power_decoder
import create_pdecode
18 from soc
.decoder
.power_decoder2
import PowerDecode2
20 from soc
.simple
.issuer
import TestIssuer
21 from soc
.experiment
.compalu_multi
import find_ok
# hack
23 from soc
.config
.test
.test_loadstore
import TestMemPspec
24 from soc
.simple
.test
.test_core
import (setup_regs
, check_regs
,
27 from soc
.fu
.compunits
.test
.test_compunit
import (setup_test_memory
,
29 from soc
.debug
.dmi
import DBGCore
, DBGCtrl
, DBGStat
31 # test with ALU data and Logical data
32 from soc
.fu
.alu
.test
.test_pipe_caller
import ALUTestCase
33 from soc
.fu
.div
.test
.test_pipe_caller
import DivTestCases
34 from soc
.fu
.logical
.test
.test_pipe_caller
import LogicalTestCase
35 #from soc.fu.shift_rot.test.test_pipe_caller import ShiftRotTestCase
36 from soc
.fu
.cr
.test
.test_pipe_caller
import CRTestCase
37 #from soc.fu.branch.test.test_pipe_caller import BranchTestCase
38 #from soc.fu.spr.test.test_pipe_caller import SPRTestCase
39 from soc
.fu
.ldst
.test
.test_pipe_caller
import LDSTTestCase
40 from soc
.simulator
.test_sim
import (GeneralTestCases
, AttnTestCase
)
41 #from soc.simulator.test_helloworld_sim import HelloTestCases
44 def setup_i_memory(imem
, startaddr
, instructions
):
46 print("insn before, init mem", mem
.depth
, mem
.width
, mem
,
48 for i
in range(mem
.depth
):
49 yield mem
._array
[i
].eq(0)
51 startaddr
//= 4 # instructions are 32-bit
54 for ins
in instructions
:
55 if isinstance(ins
, tuple):
59 insn
= insn
& 0xffffffff
60 yield mem
._array
[startaddr
].eq(insn
)
63 print("instr: %06x 0x%x %s" % (4*startaddr
, insn
, code
))
65 startaddr
= startaddr
& mask
70 for ins
in instructions
:
71 if isinstance(ins
, tuple):
75 insn
= insn
& 0xffffffff
76 msbs
= (startaddr
>> 1) & mask
77 val
= yield mem
._array
[msbs
]
79 print("before set", hex(4*startaddr
),
80 hex(msbs
), hex(val
), hex(insn
))
81 lsb
= 1 if (startaddr
& 1) else 0
82 val
= (val |
(insn
<< (lsb
*32)))
84 yield mem
._array
[msbs
].eq(val
)
87 print("after set", hex(4*startaddr
), hex(msbs
), hex(val
))
88 print("instr: %06x 0x%x %s %08x" % (4*startaddr
, insn
, code
, val
))
90 startaddr
= startaddr
& mask
93 def set_dmi(dmi
, addr
, data
):
95 yield dmi
.addr_i
.eq(addr
)
96 yield dmi
.din
.eq(data
)
104 yield dmi
.req_i
.eq(0)
105 yield dmi
.addr_i
.eq(0)
111 def get_dmi(dmi
, addr
):
112 yield dmi
.req_i
.eq(1)
113 yield dmi
.addr_i
.eq(addr
)
117 ack
= yield dmi
.ack_o
122 data
= yield dmi
.dout
# get data after ack valid for 1 cycle
123 yield dmi
.req_i
.eq(0)
124 yield dmi
.addr_i
.eq(0)
130 class TestRunner(FHDLTestCase
):
131 def __init__(self
, tst_data
):
132 super().__init
__("run_all")
133 self
.test_data
= tst_data
140 pspec
= TestMemPspec(ldst_ifacetype
='test_bare_wb',
141 imem_ifacetype
='test_bare_wb',
147 m
.submodules
.issuer
= issuer
= TestIssuer(pspec
)
148 imem
= issuer
.imem
._get
_memory
()
151 pdecode2
= issuer
.pdecode2
154 # copy of the decoder for simulator
155 simdec
= create_pdecode()
156 simdec2
= PowerDecode2(simdec
)
157 m
.submodules
.simdec2
= simdec2
# pain in the neck
159 comb
+= issuer
.pc_i
.data
.eq(pc_i
)
168 yield from set_dmi(dmi
, DBGCore
.CTRL
, 1<<DBGCtrl
.STOP
)
172 for test
in self
.test_data
:
175 #yield from set_dmi(dmi, DBGCore.CTRL, 1<<DBGCtrl.RESET)
177 # set up bigendian (TODO: don't do this, use MSR)
178 yield issuer
.core_bigendian_i
.eq(bigendian
)
187 program
= test
.program
188 self
.subTest(test
.name
)
189 print("regs", test
.regs
)
190 print("sprs", test
.sprs
)
192 print("mem", test
.mem
)
193 print("msr", test
.msr
)
194 print("assem", program
.assembly
)
195 gen
= list(program
.generate_instructions())
196 insncode
= program
.assembly
.splitlines()
197 instructions
= list(zip(gen
, insncode
))
198 sim
= ISA(simdec2
, test
.regs
, test
.sprs
, test
.cr
, test
.mem
,
200 initial_insns
=gen
, respect_pc
=True,
201 disassembly
=insncode
,
204 pc
= 0 # start address
205 counter
= 0 # test to pause/start
207 yield from setup_i_memory(imem
, pc
, instructions
)
208 yield from setup_test_memory(l0
, sim
)
209 yield from setup_regs(pdecode2
, core
, test
)
212 yield issuer
.pc_i
.ok
.eq(1)
215 print("instructions", instructions
)
217 index
= sim
.pc
.CIA
.value
//4
218 while index
< len(instructions
):
219 ins
, code
= instructions
[index
]
221 print("instruction: 0x{:X}".format(ins
& 0xffffffff))
227 yield from set_dmi(dmi
, DBGCore
.CTRL
, 1<<DBGCtrl
.START
)
228 yield issuer
.pc_i
.ok
.eq(0) # no change PC after this
232 counter
= counter
+ 1
234 # wait until executed
235 yield from wait_for_busy_hi(core
)
236 yield from wait_for_busy_clear(core
)
238 # set up simulated instruction (in simdec2)
240 yield from sim
.setup_one()
241 except KeyError: # indicates instruction not in imem: stop
245 # call simulated operation
247 yield from sim
.execute_one()
249 index
= sim
.pc
.CIA
.value
//4
251 terminated
= yield issuer
.dbg
.terminated_o
252 print("terminated", terminated
)
254 if index
>= len(instructions
):
255 print ("index over, send dmi stop")
257 yield from set_dmi(dmi
, DBGCore
.CTRL
, 1<<DBGCtrl
.STOP
)
261 # wait one cycle for registers to settle
265 yield from check_regs(self
, sim
, core
, test
, code
)
268 yield from check_sim_memory(self
, l0
, sim
, code
)
270 terminated
= yield issuer
.dbg
.terminated_o
271 print("terminated(2)", terminated
)
276 yield from set_dmi(dmi
, DBGCore
.CTRL
, 1<<DBGCtrl
.STOP
)
280 # test of dmi reg get
281 for int_reg
in range(32):
282 yield from set_dmi(dmi
, DBGCore
.GSPR_IDX
, int_reg
)
283 value
= yield from get_dmi(dmi
, DBGCore
.GSPR_DATA
)
285 print ("after test %s reg %2d value %x" % \
286 (test
.name
, int_reg
, value
))
288 sim
.add_sync_process(process
)
289 with sim
.write_vcd("issuer_simulator.vcd",
294 if __name__
== "__main__":
295 unittest
.main(exit
=False)
296 suite
= unittest
.TestSuite()
297 # suite.addTest(TestRunner(HelloTestCases.test_data))
298 suite
.addTest(TestRunner(DivTestCases().test_data
))
299 # suite.addTest(TestRunner(AttnTestCase.test_data))
300 suite
.addTest(TestRunner(GeneralTestCases
.test_data
))
301 suite
.addTest(TestRunner(LDSTTestCase().test_data
))
302 # suite.addTest(TestRunner(CRTestCase().test_data))
303 # suite.addTest(TestRunner(ShiftRotTestCase.test_data))
304 suite
.addTest(TestRunner(LogicalTestCase().test_data
))
305 suite
.addTest(TestRunner(ALUTestCase().test_data
))
306 # suite.addTest(TestRunner(BranchTestCase.test_data))
307 # suite.addTest(TestRunner(SPRTestCase.test_data))
309 runner
= unittest
.TextTestRunner()