60f049ee6d979cebce6e833c81f53155c3cc65c5
1 """TestRunner class, runs TestIssuer instructions
5 * https://bugs.libre-soc.org/show_bug.cgi?id=363
7 from nmigen
import Module
, Signal
, Cat
, ClockSignal
9 # NOTE: to use cxxsim, export NMIGEN_SIM_MODE=cxxsim from the shell
10 # Also, check out the cxxsim nmigen branch, and latest yosys from git
11 from nmutil
.sim_tmp_alternative
import Simulator
, Settle
13 from nmutil
.formaltest
import FHDLTestCase
14 from nmutil
.gtkw
import write_gtkw
15 from nmigen
.cli
import rtlil
16 from soc
.decoder
.isa
.caller
import special_sprs
, SVP64State
17 from soc
.decoder
.isa
.all
import ISA
18 from soc
.config
.endian
import bigendian
20 from soc
.decoder
.power_decoder
import create_pdecode
21 from soc
.decoder
.power_decoder2
import PowerDecode2
22 from soc
.regfile
.regfiles
import StateRegs
24 from soc
.simple
.issuer
import TestIssuerInternal
26 from soc
.config
.test
.test_loadstore
import TestMemPspec
27 from soc
.simple
.test
.test_core
import (setup_regs
, check_regs
,
30 from soc
.fu
.compunits
.test
.test_compunit
import (setup_test_memory
,
32 from soc
.debug
.dmi
import DBGCore
, DBGCtrl
, DBGStat
35 def setup_i_memory(imem
, startaddr
, instructions
):
37 print("insn before, init mem", mem
.depth
, mem
.width
, mem
,
39 for i
in range(mem
.depth
):
40 yield mem
._array
[i
].eq(0)
42 startaddr
//= 4 # instructions are 32-bit
45 for ins
in instructions
:
46 if isinstance(ins
, tuple):
50 insn
= insn
& 0xffffffff
51 yield mem
._array
[startaddr
].eq(insn
)
54 print("instr: %06x 0x%x %s" % (4*startaddr
, insn
, code
))
56 startaddr
= startaddr
& mask
61 for ins
in instructions
:
62 if isinstance(ins
, tuple):
66 insn
= insn
& 0xffffffff
67 msbs
= (startaddr
>> 1) & mask
68 val
= yield mem
._array
[msbs
]
70 print("before set", hex(4*startaddr
),
71 hex(msbs
), hex(val
), hex(insn
))
72 lsb
= 1 if (startaddr
& 1) else 0
73 val
= (val |
(insn
<< (lsb
*32)))
75 yield mem
._array
[msbs
].eq(val
)
78 print("after set", hex(4*startaddr
), hex(msbs
), hex(val
))
79 print("instr: %06x 0x%x %s %08x" % (4*startaddr
, insn
, code
, val
))
81 startaddr
= startaddr
& mask
84 def set_dmi(dmi
, addr
, data
):
86 yield dmi
.addr_i
.eq(addr
)
87 yield dmi
.din
.eq(data
)
96 yield dmi
.addr_i
.eq(0)
102 def get_dmi(dmi
, addr
):
103 yield dmi
.req_i
.eq(1)
104 yield dmi
.addr_i
.eq(addr
)
108 ack
= yield dmi
.ack_o
113 data
= yield dmi
.dout
# get data after ack valid for 1 cycle
114 yield dmi
.req_i
.eq(0)
115 yield dmi
.addr_i
.eq(0)
121 class TestRunner(FHDLTestCase
):
122 def __init__(self
, tst_data
, microwatt_mmu
=False, rom
=None):
123 super().__init
__("run_all")
124 self
.test_data
= tst_data
125 self
.microwatt_mmu
= microwatt_mmu
133 pspec
= TestMemPspec(ldst_ifacetype
='test_bare_wb',
134 imem_ifacetype
='test_bare_wb',
143 mmu
=self
.microwatt_mmu
,
145 m
.submodules
.issuer
= issuer
= TestIssuerInternal(pspec
)
146 imem
= issuer
.imem
._get
_memory
()
149 pdecode2
= issuer
.pdecode2
152 # copy of the decoder for simulator
153 simdec
= create_pdecode()
154 simdec2
= PowerDecode2(simdec
)
155 m
.submodules
.simdec2
= simdec2
# pain in the neck
157 # run core clock at same rate as test clock
158 intclk
= ClockSignal("coresync")
159 comb
+= intclk
.eq(ClockSignal())
161 comb
+= issuer
.pc_i
.data
.eq(pc_i
)
170 yield from set_dmi(dmi
, DBGCore
.CTRL
, 1<<DBGCtrl
.STOP
)
174 # get each test, completely reset the core, and run it
176 for test
in self
.test_data
:
179 # yield from set_dmi(dmi, DBGCore.CTRL, 1<<DBGCtrl.RESET)
181 # set up bigendian (TODO: don't do this, use MSR)
182 yield issuer
.core_bigendian_i
.eq(bigendian
)
191 program
= test
.program
192 self
.subTest(test
.name
)
193 print("regs", test
.regs
)
194 print("sprs", test
.sprs
)
196 print("mem", test
.mem
)
197 print("msr", test
.msr
)
198 print("assem", program
.assembly
)
199 gen
= list(program
.generate_instructions())
200 insncode
= program
.assembly
.splitlines()
201 instructions
= list(zip(gen
, insncode
))
203 # set up the Simulator (which must track TestIssuer exactly)
204 sim
= ISA(simdec2
, test
.regs
, test
.sprs
, test
.cr
, test
.mem
,
206 initial_insns
=gen
, respect_pc
=True,
207 disassembly
=insncode
,
209 initial_svstate
=test
.svstate
)
211 # establish the TestIssuer context (mem, regs etc)
213 pc
= 0 # start address
214 counter
= 0 # test to pause/start
216 yield from setup_i_memory(imem
, pc
, instructions
)
217 yield from setup_test_memory(l0
, sim
)
218 yield from setup_regs(pdecode2
, core
, test
)
219 # TODO, setup svstate here in core.regs.state regfile
220 # https://bugs.libre-soc.org/show_bug.cgi?id=583#c35
222 initial_svstate
= test
.svstate
223 if isinstance(initial_svstate
, int):
224 initial_svstate
= SVP64State(initial_svstate
)
225 svstate_reg
= core
.regs
.state
.regs
[StateRegs
.SVSTATE
].reg
226 yield svstate_reg
.eq(initial_svstate
.spr
.value
)
229 yield issuer
.pc_i
.ok
.eq(1)
232 print("instructions", instructions
)
234 # run the loop of the instructions on the current test
235 index
= sim
.pc
.CIA
.value
//4
236 while index
< len(instructions
):
237 ins
, code
= instructions
[index
]
239 print("instruction: 0x{:X}".format(ins
& 0xffffffff))
245 yield from set_dmi(dmi
, DBGCore
.CTRL
, 1<<DBGCtrl
.START
)
246 yield issuer
.pc_i
.ok
.eq(0) # no change PC after this
250 counter
= counter
+ 1
252 # wait until executed
253 yield from wait_for_busy_hi(core
)
254 yield from wait_for_busy_clear(core
)
256 # set up simulated instruction (in simdec2)
258 yield from sim
.setup_one()
259 except KeyError: # indicates instruction not in imem: stop
263 # call simulated operation
265 yield from sim
.execute_one()
267 index
= sim
.pc
.CIA
.value
//4
269 terminated
= yield issuer
.dbg
.terminated_o
270 print("terminated", terminated
)
272 if index
>= len(instructions
):
273 print ("index over, send dmi stop")
275 yield from set_dmi(dmi
, DBGCore
.CTRL
, 1<<DBGCtrl
.STOP
)
279 # wait one cycle for registers to settle
283 yield from check_regs(self
, sim
, core
, test
, code
)
286 yield from check_sim_memory(self
, l0
, sim
, code
)
288 terminated
= yield issuer
.dbg
.terminated_o
289 print("terminated(2)", terminated
)
294 yield from set_dmi(dmi
, DBGCore
.CTRL
, 1<<DBGCtrl
.STOP
)
299 cr
= yield from get_dmi(dmi
, DBGCore
.CR
)
300 print("after test %s cr value %x" % (test
.name
, cr
))
303 xer
= yield from get_dmi(dmi
, DBGCore
.XER
)
304 print("after test %s XER value %x" % (test
.name
, xer
))
306 # test of dmi reg get
307 for int_reg
in range(32):
308 yield from set_dmi(dmi
, DBGCore
.GSPR_IDX
, int_reg
)
309 value
= yield from get_dmi(dmi
, DBGCore
.GSPR_DATA
)
311 print("after test %s reg %2d value %x" %
312 (test
.name
, int_reg
, value
))
315 'dec': {'base': 'dec'},
316 'bin': {'base': 'bin'}
321 {'comment': 'state machines'},
322 'fetch_pc_valid_i', 'fetch_pc_ready_o', 'fetch_fsm_state',
323 'fetch_insn_valid_o', 'fetch_insn_ready_i', 'fsm_state',
324 {'comment': 'fetch and decode'},
325 'cia[63:0]', 'nia[63:0]', 'pc[63:0]', 'raw_insn_i[31:0]',
326 'raw_opcode_in[31:0]', 'insn_type',
327 {'comment': 'svp64 decoding'},
329 ('dec2.extra[8:0]', 'bin'),
330 ('register augmentation', 'dec', [
331 {'comment': 'v3.0b registers'},
332 'dec2.dec_o.RT[4:0]',
333 'dec2.dec_a.RA[4:0]',
334 'dec2.dec_b.RB[4:0]',
336 'dec2.o_svdec.reg_in[4:0]',
337 ('dec2.o_svdec.spec[2:0]', 'bin'),
338 'dec2.o_svdec.reg_out[6:0]']),
340 'dec2.in1_svdec.reg_in[4:0]',
341 ('dec2.in1_svdec.spec[2:0]', 'bin'),
342 'dec2.in1_svdec.reg_out[6:0]']),
344 'dec2.in2_svdec.reg_in[4:0]',
345 ('dec2.in2_svdec.spec[2:0]', 'bin'),
346 'dec2.in2_svdec.reg_out[6:0]']),
347 {'comment': 'SVP64 registers'},
348 'dec2.rego[6:0]', 'dec2.reg1[6:0]', 'dec2.reg2[6:0]'
350 {'comment': 'svp64 context'},
351 'core_core_vl[6:0]', 'core_core_maxvl[6:0]',
352 'core_core_srcstep[6:0]', 'core_core_dststep[6:0]',
353 {'comment': 'issue and execute'},
354 'core.core_core_insn_type',
356 'core_rego[6:0]', 'core_reg1[6:0]', 'core_reg2[6:0]']),
359 'dbg.dmi_req_i', 'dbg.dmi_ack_o',
360 {'comment': 'instruction memory'},
361 'imem.sram.rdport.memory(0)[63:0]',
362 {'comment': 'registers'},
363 'core.int.rp_src1.memory(0)[63:0]',
364 'core.int.rp_src1.memory(1)[63:0]',
365 'core.int.rp_src1.memory(2)[63:0]',
366 'core.int.rp_src1.memory(3)[63:0]',
367 'core.int.rp_src1.memory(4)[63:0]',
368 'core.int.rp_src1.memory(5)[63:0]',
369 'core.int.rp_src1.memory(6)[63:0]',
370 'core.int.rp_src1.memory(7)[63:0]',
371 'core.int.rp_src1.memory(9)[63:0]',
372 'core.int.rp_src1.memory(10)[63:0]',
373 'core.int.rp_src1.memory(13)[63:0]',
376 if self
.microwatt_mmu
:
378 {'comment': 'microwatt_mmu'},
379 'core.fus.mmu0.alu_mmu0.illegal',
380 'core.fus.mmu0.alu_mmu0.debug0[3:0]',
381 'core.fus.mmu0.alu_mmu0.mmu.state',
382 'core.fus.mmu0.alu_mmu0.mmu.pid[31:0]',
383 'core.fus.mmu0.alu_mmu0.mmu.prtbl[63:0]',
384 {'comment': 'wishbone_memory'},
385 'core.fus.mmu0.alu_mmu0.dcache.stb',
386 'core.fus.mmu0.alu_mmu0.dcache.cyc',
387 'core.fus.mmu0.alu_mmu0.dcache.we',
388 'core.fus.mmu0.alu_mmu0.dcache.ack',
389 'core.fus.mmu0.alu_mmu0.dcache.stall,'
392 write_gtkw("issuer_simulator.gtkw",
393 "issuer_simulator.vcd",
394 traces
, styles
, module
='top.issuer')
396 # add run of instructions
397 sim
.add_sync_process(process
)
399 # optionally, if a wishbone-based ROM is passed in, run that as an
400 # extra emulated process
401 if self
.rom
is not None:
402 dcache
= core
.fus
.fus
["mmu0"].alu
.dcache
403 default_mem
= self
.rom
404 sim
.add_sync_process(wrap(wb_get(dcache
, default_mem
, "DCACHE")))
406 with sim
.write_vcd("issuer_simulator.vcd"):