src/soc/simple/test/test_runner.py

   1 """TestRunner class, runs TestIssuer instructions
   2
   3 related bugs:
   4
   5  * https://bugs.libre-soc.org/show_bug.cgi?id=363
   6  * https://bugs.libre-soc.org/show_bug.cgi?id=686#c51
   7 """
   8 from nmigen import Module, Signal
   9 from nmigen.hdl.xfrm import ResetInserter
  10 from copy import copy
  11
  12 # NOTE: to use cxxsim, export NMIGEN_SIM_MODE=cxxsim from the shell
  13 # Also, check out the cxxsim nmigen branch, and latest yosys from git
  14 from nmutil.sim_tmp_alternative import Simulator, Settle
  15
  16 from openpower.decoder.isa.caller import SVP64State
  17 from openpower.decoder.isa.all import ISA
  18 from openpower.endian import bigendian
  19
  20 from soc.simple.issuer import TestIssuerInternal
  21
  22 from soc.simple.test.test_core import (setup_regs, check_regs, check_mem,
  23                                        wait_for_busy_clear,
  24                                        wait_for_busy_hi)
  25 from soc.fu.compunits.test.test_compunit import (setup_tst_memory,
  26                                                  check_sim_memory)
  27 from soc.debug.dmi import DBGCore, DBGCtrl, DBGStat
  28 from nmutil.util import wrap
  29 from openpower.test.state import TestState, StateRunner
  30 from openpower.test.runner import TestRunnerBase
  31
  32
  33 def setup_i_memory(imem, startaddr, instructions):
  34     mem = imem
  35     print("insn before, init mem", mem.depth, mem.width, mem,
  36           len(instructions))
  37     for i in range(mem.depth):
  38         yield mem._array[i].eq(0)
  39     yield Settle()
  40     startaddr //= 4  # instructions are 32-bit
  41     if mem.width == 32:
  42         mask = ((1 << 32)-1)
  43         for ins in instructions:
  44             if isinstance(ins, tuple):
  45                 insn, code = ins
  46             else:
  47                 insn, code = ins, ''
  48             insn = insn & 0xffffffff
  49             yield mem._array[startaddr].eq(insn)
  50             yield Settle()
  51             if insn != 0:
  52                 print("instr: %06x 0x%x %s" % (4*startaddr, insn, code))
  53             startaddr += 1
  54             startaddr = startaddr & mask
  55         return
  56
  57     # 64 bit
  58     mask = ((1 << 64)-1)
  59     for ins in instructions:
  60         if isinstance(ins, tuple):
  61             insn, code = ins
  62         else:
  63             insn, code = ins, ''
  64         insn = insn & 0xffffffff
  65         msbs = (startaddr >> 1) & mask
  66         val = yield mem._array[msbs]
  67         if insn != 0:
  68             print("before set", hex(4*startaddr),
  69                   hex(msbs), hex(val), hex(insn))
  70         lsb = 1 if (startaddr & 1) else 0
  71         val = (val | (insn << (lsb*32)))
  72         val = val & mask
  73         yield mem._array[msbs].eq(val)
  74         yield Settle()
  75         if insn != 0:
  76             print("after  set", hex(4*startaddr), hex(msbs), hex(val))
  77             print("instr: %06x 0x%x %s %08x" % (4*startaddr, insn, code, val))
  78         startaddr += 1
  79         startaddr = startaddr & mask
  80
  81
  82 def set_dmi(dmi, addr, data):
  83     yield dmi.req_i.eq(1)
  84     yield dmi.addr_i.eq(addr)
  85     yield dmi.din.eq(data)
  86     yield dmi.we_i.eq(1)
  87     while True:
  88         ack = yield dmi.ack_o
  89         if ack:
  90             break
  91         yield
  92     yield
  93     yield dmi.req_i.eq(0)
  94     yield dmi.addr_i.eq(0)
  95     yield dmi.din.eq(0)
  96     yield dmi.we_i.eq(0)
  97     yield
  98
  99
 100 def get_dmi(dmi, addr):
 101     yield dmi.req_i.eq(1)
 102     yield dmi.addr_i.eq(addr)
 103     yield dmi.din.eq(0)
 104     yield dmi.we_i.eq(0)
 105     while True:
 106         ack = yield dmi.ack_o
 107         if ack:
 108             break
 109         yield
 110     yield  # wait one
 111     data = yield dmi.dout  # get data after ack valid for 1 cycle
 112     yield dmi.req_i.eq(0)
 113     yield dmi.addr_i.eq(0)
 114     yield dmi.we_i.eq(0)
 115     yield
 116     return data
 117
 118
 119 class HDLRunner(StateRunner):
 120     """HDLRunner:  Implements methods for the setup, preparation, and
 121     running of tests using nmigen HDL simulation.
 122     """
 123     def __init__(self, dut, m, pspec):
 124         super().__init__("hdl", HDLRunner)
 125
 126         self.dut = dut
 127         self.pc_i = Signal(32)
 128         self.svstate_i = Signal(64)
 129
 130         #hard_reset = Signal(reset_less=True)
 131         self.issuer = TestIssuerInternal(pspec)
 132         # use DMI RESET command instead, this does actually work though
 133         #issuer = ResetInserter({'coresync': hard_reset,
 134         #                        'sync': hard_reset})(issuer)
 135         m.submodules.issuer = self.issuer
 136         self.dmi = self.issuer.dbg.dmi
 137
 138         comb = m.d.comb
 139         comb += self.issuer.pc_i.data.eq(self.pc_i)
 140         comb += self.issuer.svstate_i.data.eq(self.svstate_i)
 141
 142     def prepare_for_test(self, test):
 143         self.test = test
 144
 145         # set up bigendian (TODO: don't do this, use MSR)
 146         yield self.issuer.core_bigendian_i.eq(bigendian)
 147         yield Settle()
 148
 149         yield
 150         yield
 151         yield
 152         yield
 153
 154     def setup_during_test(self):
 155         yield from set_dmi(self.dmi, DBGCore.CTRL, 1<<DBGCtrl.STOP)
 156         yield
 157
 158     def run_test(self, instructions):
 159         """run_hdl_state - runs a TestIssuer nmigen HDL simulation
 160         """
 161
 162         imem = self.issuer.imem._get_memory()
 163         core = self.issuer.core
 164         dmi = self.issuer.dbg.dmi
 165         pdecode2 = self.issuer.pdecode2
 166         l0 = core.l0
 167         hdl_states = []
 168
 169         # establish the TestIssuer context (mem, regs etc)
 170
 171         pc = 0  # start address
 172         counter = 0  # test to pause/start
 173
 174         yield from setup_i_memory(imem, pc, instructions)
 175         yield from setup_tst_memory(l0, self.test.mem)
 176         yield from setup_regs(pdecode2, core, self.test)
 177
 178         # set PC and SVSTATE
 179         yield self.pc_i.eq(pc)
 180         yield self.issuer.pc_i.ok.eq(1)
 181
 182         # copy initial SVSTATE
 183         initial_svstate = copy(self.test.svstate)
 184         if isinstance(initial_svstate, int):
 185             initial_svstate = SVP64State(initial_svstate)
 186         yield self.svstate_i.eq(initial_svstate.value)
 187         yield self.issuer.svstate_i.ok.eq(1)
 188         yield
 189
 190         print("instructions", instructions)
 191
 192         # run the loop of the instructions on the current test
 193         index = (yield self.issuer.cur_state.pc) // 4
 194         while index < len(instructions):
 195             ins, code = instructions[index]
 196
 197             print("hdl instr: 0x{:X}".format(ins & 0xffffffff))
 198             print(index, code)
 199
 200             if counter == 0:
 201                 # start the core
 202                 yield
 203                 yield from set_dmi(dmi, DBGCore.CTRL,
 204                                 1<<DBGCtrl.START)
 205                 yield self.issuer.pc_i.ok.eq(0) # no change PC after this
 206                 yield self.issuer.svstate_i.ok.eq(0) # ditto
 207                 yield
 208                 yield
 209
 210             counter = counter + 1
 211
 212             # wait until executed
 213             while not (yield self.issuer.insn_done):
 214                 yield
 215
 216             # okaaay long story: in overlap mode, PC is updated one cycle
 217             # late.
 218             if self.dut.allow_overlap:
 219                 yield
 220             yield Settle()
 221
 222             index = (yield self.issuer.cur_state.pc) // 4
 223
 224             terminated = yield self.issuer.dbg.terminated_o
 225             print("terminated", terminated, index, len(instructions))
 226
 227             if index < len(instructions):
 228                 # Get HDL mem and state
 229                 state = yield from TestState("hdl", core, self.dut,
 230                                             code)
 231                 hdl_states.append(state)
 232
 233             if index >= len(instructions):
 234                 print ("index over, send dmi stop")
 235                 # stop at end
 236                 yield from set_dmi(dmi, DBGCore.CTRL, 1<<DBGCtrl.STOP)
 237                 yield
 238                 yield
 239
 240             terminated = yield self.issuer.dbg.terminated_o
 241             print("terminated(2)", terminated)
 242             if terminated:
 243                 break
 244
 245         if self.dut.allow_overlap:
 246             # wait until all settled
 247             # XXX really this should be in DMI, which should in turn
 248             # use issuer.any_busy to not send back "stopped" signal
 249             while (yield self.issuer.any_busy):
 250                 yield
 251
 252         if self.dut.allow_overlap:
 253             # get last state, at end of run
 254             state = yield from TestState("hdl", core, self.dut,
 255                                         code)
 256             hdl_states.append(state)
 257
 258         return hdl_states
 259
 260     def end_test(self):
 261         yield from set_dmi(self.dmi, DBGCore.CTRL, 1<<DBGCtrl.STOP)
 262         yield
 263         yield
 264
 265         # TODO, here is where the static (expected) results
 266         # can be checked: register check (TODO, memory check)
 267         # see https://bugs.libre-soc.org/show_bug.cgi?id=686#c51
 268         # yield from check_regs(self, sim, core, test, code,
 269         #                       >>>expected_data<<<)
 270
 271         # get CR
 272         cr = yield from get_dmi(self.dmi, DBGCore.CR)
 273         print("after test %s cr value %x" % (self.test.name, cr))
 274
 275         # get XER
 276         xer = yield from get_dmi(self.dmi, DBGCore.XER)
 277         print("after test %s XER value %x" % (self.test.name, xer))
 278
 279         # test of dmi reg get
 280         for int_reg in range(32):
 281             yield from set_dmi(self.dmi, DBGCore.GSPR_IDX, int_reg)
 282             value = yield from get_dmi(self.dmi, DBGCore.GSPR_DATA)
 283
 284             print("after test %s reg %2d value %x" %
 285             (self.test.name, int_reg, value))
 286
 287         # pull a reset
 288         yield from set_dmi(self.dmi, DBGCore.CTRL, 1<<DBGCtrl.RESET)
 289         yield
 290
 291
 292 class TestRunner(TestRunnerBase):
 293     def __init__(self, tst_data, microwatt_mmu=False, rom=None,
 294                         svp64=True, run_hdl=True, run_sim=True,
 295                         allow_overlap=False):
 296         if run_hdl:
 297             run_hdl = HDLRunner
 298         super().__init__(tst_data, microwatt_mmu=microwatt_mmu,
 299                         rom=rom,
 300                         svp64=svp64, run_hdl=run_hdl, run_sim=run_sim,
 301                         allow_overlap=allow_overlap)
 302