068beacd8a1f6d25ce33b00efc661601b5d5152d
1 from nmigen
import Module
, Signal
2 from nmigen
.back
.pysim
import Simulator
, Delay
3 from nmigen
.test
.utils
import FHDLTestCase
5 from soc
.simulator
.internalop_sim
import InternalOpSimulator
6 from soc
.decoder
.power_decoder
import (create_pdecode
)
7 from soc
.decoder
.power_enums
import (Function
, InternalOp
,
8 In1Sel
, In2Sel
, In3Sel
,
9 OutSel
, RC
, LdstLen
, CryIn
,
10 single_bit_flags
, Form
, SPR
,
11 get_signal_name
, get_csv
)
12 from soc
.decoder
.power_decoder2
import (PowerDecode2
)
13 from soc
.simulator
.program
import Program
14 from soc
.simulator
.qemu
import run_program
18 def __init__(self
, num
):
22 class DecoderTestCase(FHDLTestCase
):
24 def run_tst(self
, generator
, simulator
):
27 instruction
= Signal(32)
29 pdecode
= create_pdecode()
31 m
.submodules
.pdecode2
= pdecode2
= PowerDecode2(pdecode
)
32 comb
+= pdecode2
.dec
.raw_opcode_in
.eq(instruction
)
34 gen
= generator
.generate_instructions()
39 print("0x{:X}".format(ins
& 0xffffffff))
41 # ask the decoder to decode this binary data (endian'd)
42 yield pdecode2
.dec
.bigendian
.eq(0) # little / big?
43 yield instruction
.eq(ins
) # raw binary instr.
45 yield from simulator
.execute_op(pdecode2
)
47 sim
.add_process(process
)
48 with sim
.write_vcd("simulator.vcd", "simulator.gtkw",
49 traces
=pdecode2
.ports()):
52 def test_example(self
):
53 lst
= ["addi 1, 0, 0x1234",
57 with
Program(lst
) as program
:
58 self
.run_tst_program(program
, [1, 2, 3, 4])
61 lst
= ["addi 1, 0, 0x1234",
65 with
Program(lst
) as program
:
66 self
.run_tst_program(program
, [1, 2, 3])
68 def test_ldst_extended(self
):
69 lst
= ["addi 1, 0, 0x1234",
74 with
Program(lst
) as program
:
75 self
.run_tst_program(program
, [1, 2, 3])
77 def test_ldst_widths(self
):
78 lst
= [" lis 1, 0xdead",
88 with
Program(lst
) as program
:
89 self
.run_tst_program(program
, [1, 2, 3, 4, 5])
92 lst
= ["addi 1, 0, 0x1234",
95 "subfic 4, 1, 0x1337",
97 with
Program(lst
) as program
:
98 self
.run_tst_program(program
, [1, 2, 3, 4, 5])
100 def run_tst_program(self
, prog
, reglist
):
101 simulator
= InternalOpSimulator()
102 self
.run_tst(prog
, simulator
)
104 with
run_program(prog
) as q
:
105 qemu_register_compare(simulator
, q
, reglist
)
108 def qemu_register_compare(simulator
, qemu
, regs
):
110 qemu_val
= qemu
.get_register(reg
)
111 simulator
.regfile
.assert_gpr(reg
, qemu_val
)
114 if __name__
== "__main__":