1 from nmigen
import Module
, Signal
2 from nmigen
.back
.pysim
import Simulator
, Delay
3 from nmigen
.test
.utils
import FHDLTestCase
5 from soc
.simulator
.internalop_sim
import InternalOpSimulator
6 from soc
.decoder
.power_decoder
import (create_pdecode
)
7 from soc
.decoder
.power_enums
import (Function
, InternalOp
,
8 In1Sel
, In2Sel
, In3Sel
,
9 OutSel
, RC
, LdstLen
, CryIn
,
10 single_bit_flags
, Form
, SPR
,
11 get_signal_name
, get_csv
)
12 from soc
.decoder
.power_decoder2
import (PowerDecode2
)
13 from soc
.simulator
.gas
import get_assembled_instruction
17 def __init__(self
, num
):
22 def __init__(self
, lst
):
23 self
.instrs
= [x
+ "\n" for x
in lst
]
25 def generate_instructions(self
):
26 return iter(self
.instrs
)
29 class DecoderTestCase(FHDLTestCase
):
31 def run_tst(self
, generator
, simulator
):
34 instruction
= Signal(32)
36 pdecode
= create_pdecode()
38 m
.submodules
.pdecode2
= pdecode2
= PowerDecode2(pdecode
)
39 comb
+= pdecode2
.dec
.raw_opcode_in
.eq(instruction
)
41 gen
= generator
.generate_instructions()
45 print("instr", ins
.strip())
47 # turn the instruction into binary data (endian'd)
48 ibin
= get_assembled_instruction(ins
, 0)
50 # ask the decoder to decode this binary data (endian'd)
51 yield pdecode2
.dec
.bigendian
.eq(0) # little / big?
52 yield instruction
.eq(ibin
) # raw binary instr.
54 yield from simulator
.execute_op(pdecode2
)
56 sim
.add_process(process
)
57 with sim
.write_vcd("simulator.vcd", "simulator.gtkw",
58 traces
=[pdecode2
.ports()]):
61 def test_example(self
):
62 lst
= ["addi 1, 0, 0x1234",
68 simulator
= InternalOpSimulator()
70 self
.run_tst(gen
, simulator
)
71 simulator
.regfile
.assert_gprs(
78 lst
= ["addi 1, 0, 0x1234",
84 simulator
= InternalOpSimulator()
86 self
.run_tst(gen
, simulator
)
87 simulator
.regfile
.assert_gprs(
93 if __name__
== "__main__":