76fc17f6a96076481f8d5f7b747b3380699f3baa
1 from nmigen
import Module
, Signal
2 from nmigen
.back
.pysim
import Simulator
, Delay
, Settle
3 from nmigen
.test
.utils
import FHDLTestCase
5 from soc
.decoder
.power_decoder
import (create_pdecode
)
6 from soc
.decoder
.power_enums
import (Function
, InternalOp
,
7 In1Sel
, In2Sel
, In3Sel
,
8 OutSel
, RC
, LdstLen
, CryIn
,
9 single_bit_flags
, Form
, SPR
,
10 get_signal_name
, get_csv
)
11 from soc
.decoder
.power_decoder2
import (PowerDecode2
)
12 from soc
.simulator
.program
import Program
13 from soc
.simulator
.qemu
import run_program
14 from soc
.decoder
.isa
.all
import ISA
18 def __init__(self
, num
):
22 class DecoderTestCase(FHDLTestCase
):
24 def run_tst(self
, generator
):
27 instruction
= Signal(32)
29 pdecode
= create_pdecode()
31 m
.submodules
.pdecode2
= pdecode2
= PowerDecode2(pdecode
)
33 simulator
= ISA(pdecode2
, [0] * 32, {}, 0, {}, 0)
34 comb
+= pdecode2
.dec
.raw_opcode_in
.eq(instruction
)
35 comb
+= pdecode2
.dec
.bigendian
.eq(0)
36 gen
= generator
.generate_instructions()
37 instructions
= list(zip(gen
, generator
.assembly
.splitlines()))
42 index
= simulator
.pc
.CIA
.value
//4
43 while index
< len(instructions
):
44 ins
, code
= instructions
[index
]
46 print("0x{:X}".format(ins
& 0xffffffff))
49 yield instruction
.eq(ins
)
52 opname
= code
.split(' ')[0]
53 yield from simulator
.call(opname
)
54 index
= simulator
.pc
.CIA
.value
//4
57 sim
.add_process(process
)
58 with sim
.write_vcd("simulator.vcd", "simulator.gtkw",
65 lst
= ["addi 6, 0, 0x10",
70 with
Program(lst
) as program
:
71 self
.run_tst_program(program
, [1])
73 def test_example(self
):
74 lst
= ["addi 1, 0, 0x1234",
78 with
Program(lst
) as program
:
79 self
.run_tst_program(program
, [1, 2, 3, 4])
82 lst
= ["addi 1, 0, 0x1234",
86 with
Program(lst
) as program
:
87 self
.run_tst_program(program
, [1, 2, 3])
89 def test_ldst_extended(self
):
90 lst
= ["addi 1, 0, 0x1234",
95 with
Program(lst
) as program
:
96 self
.run_tst_program(program
, [1, 2, 3])
98 def test_0_ldst_widths(self
):
99 lst
= ["addis 1, 0, 0xdead",
109 with
Program(lst
) as program
:
110 self
.run_tst_program(program
, [1, 2, 3, 4, 5])
113 lst
= ["addi 1, 0, 0x1234",
116 "subfic 4, 1, 0x1337",
118 with
Program(lst
) as program
:
119 self
.run_tst_program(program
, [1, 2, 3, 4, 5])
121 def test_add_with_carry(self
):
122 lst
= ["addi 1, 0, 5",
129 with
Program(lst
) as program
:
130 self
.run_tst_program(program
, [1, 2, 3])
132 def test_addis(self
):
133 lst
= ["addi 1, 0, 0x0FFF",
136 with
Program(lst
) as program
:
137 self
.run_tst_program(program
, [1])
139 @unittest.skip("broken")
140 def test_mulli(self
):
141 lst
= ["addi 1, 0, 3",
144 with
Program(lst
) as program
:
145 self
.run_tst_program(program
, [1])
147 def run_tst_program(self
, prog
, reglist
):
149 simulator
= self
.run_tst(prog
)
151 with
run_program(prog
) as q
:
152 self
.qemu_register_compare(simulator
, q
, reglist
)
153 self
.qemu_mem_compare(simulator
, q
, reglist
)
154 print(simulator
.gpr
.dump())
156 def qemu_mem_compare(self
, sim
, qemu
, regs
):
158 qmemdump
= qemu
.get_mem(addr
, 16)
159 for i
in range(len(qmemdump
)):
160 s
= hex(int(qmemdump
[i
]))
161 print ("qemu mem %06x %s" % (addr
+i
*8, s
))
162 for k
, v
in sim
.mem
.mem
.items():
163 print ("sim %06x %016x" % (k
, v
))
164 for k
, v
in sim
.mem
.mem
.items():
165 self
.assertEqual(int(qmemdump
[(k
-0x200)//8]), v
) # magic constant??
167 def qemu_register_compare(self
, sim
, qemu
, regs
):
168 qpc
, qxer
, qcr
= qemu
.get_pc(), qemu
.get_xer(), qemu
.get_cr()
169 sim_cr
= sim
.cr
.get_range().value
170 sim_pc
= sim
.pc
.CIA
.value
171 sim_xer
= sim
.spr
['XER'].value
172 print("qemu pc", hex(qpc
))
173 print("qemu cr", hex(qcr
))
174 print("qemu xer", bin(qxer
))
175 print("sim pc", hex(sim
.pc
.CIA
.value
))
176 print("sim cr", hex(sim_cr
))
177 print("sim xer", hex(sim_xer
))
178 self
.assertEqual(qcr
, sim_cr
)
180 qemu_val
= qemu
.get_register(reg
)
181 sim_val
= sim
.gpr(reg
).value
182 self
.assertEqual(qemu_val
, sim_val
)
185 if __name__
== "__main__":