src/soc/simulator/test_sim.py

   1 from nmigen import Module, Signal
   2 from nmigen.back.pysim import Simulator, Delay, Settle
   3 from nmigen.test.utils import FHDLTestCase
   4 import unittest
   5 from soc.decoder.power_decoder import (create_pdecode)
   6 from soc.decoder.power_enums import (Function, InternalOp,
   7                                      In1Sel, In2Sel, In3Sel,
   8                                      OutSel, RC, LdstLen, CryIn,
   9                                      single_bit_flags, Form, SPR,
  10                                      get_signal_name, get_csv)
  11 from soc.decoder.power_decoder2 import (PowerDecode2)
  12 from soc.simulator.program import Program
  13 from soc.simulator.qemu import run_program
  14 from soc.decoder.isa.all import ISA
  15
  16
  17 class Register:
  18     def __init__(self, num):
  19         self.num = num
  20
  21
  22 class DecoderTestCase(FHDLTestCase):
  23
  24     def run_tst(self, generator):
  25         m = Module()
  26         comb = m.d.comb
  27         instruction = Signal(32)
  28
  29         pdecode = create_pdecode()
  30
  31         m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
  32
  33         simulator = ISA(pdecode2, [0] * 32, {}, 0, {}, 0)
  34         comb += pdecode2.dec.raw_opcode_in.eq(instruction)
  35         comb += pdecode2.dec.bigendian.eq(0)
  36         gen = generator.generate_instructions()
  37         instructions = list(zip(gen, generator.assembly.splitlines()))
  38
  39         sim = Simulator(m)
  40         def process():
  41
  42             index = simulator.pc.CIA.value//4
  43             while index < len(instructions):
  44                 ins, code = instructions[index]
  45
  46                 print("0x{:X}".format(ins & 0xffffffff))
  47                 print(code)
  48
  49                 yield instruction.eq(ins)
  50                 yield Delay(1e-6)
  51
  52                 opname = code.split(' ')[0]
  53                 yield from simulator.call(opname)
  54                 index = simulator.pc.CIA.value//4
  55
  56
  57         sim.add_process(process)
  58         with sim.write_vcd("simulator.vcd", "simulator.gtkw",
  59                            traces=[]):
  60             sim.run()
  61
  62         return simulator
  63
  64     def test_example(self):
  65         lst = ["addi 1, 0, 0x1234",
  66                "addi 2, 0, 0x5678",
  67                "add  3, 1, 2",
  68                "and  4, 1, 2"]
  69         with Program(lst) as program:
  70             self.run_tst_program(program, [1, 2, 3, 4])
  71
  72     def test_ldst(self):
  73         lst = ["addi 1, 0, 0x1234",
  74                "addi 2, 0, 0x5678",
  75                "stw  1, 0(2)",
  76                "lwz  3, 0(2)"]
  77         with Program(lst) as program:
  78             self.run_tst_program(program, [1, 2, 3])
  79
  80     def test_ldst_extended(self):
  81         lst = ["addi 1, 0, 0x1234",
  82                "addi 2, 0, 0x5678",
  83                "addi 4, 0, 0x40",
  84                "stw  1, 0x40(2)",
  85                "lwzx  3, 4, 2"]
  86         with Program(lst) as program:
  87             self.run_tst_program(program, [1, 2, 3])
  88
  89     def test_ldst_widths(self):
  90         lst = ["addis 1, 0, 0xdead",
  91                "ori 1, 1, 0xbeef",
  92                "addi 2, 0, 0x1000",
  93                "std 1, 0(2)",
  94                "lbz 1, 5(2)",
  95                "lhz 3, 4(2)",
  96                "lwz 4, 4(2)",
  97                "addi 5, 0, 0x12",
  98                "stb 5, 5(2)",
  99                "ld  5, 0(2)"]
 100         with Program(lst) as program:
 101             self.run_tst_program(program, [1, 2, 3, 4, 5])
 102
 103     def test_sub(self):
 104         lst = ["addi 1, 0, 0x1234",
 105                "addi 2, 0, 0x5678",
 106                "subf 3, 1, 2",
 107                "subfic 4, 1, 0x1337",
 108                "neg 5, 1"]
 109         with Program(lst) as program:
 110             self.run_tst_program(program, [1, 2, 3, 4, 5])
 111
 112     def test_add_with_carry(self):
 113         lst = ["addi 1, 0, 5",
 114                "neg 1, 1",
 115                "addi 2, 0, 7",
 116                "neg 2, 2",
 117                "addc 3, 2, 1",
 118                "addi 3, 3, 1"
 119                ]
 120         with Program(lst) as program:
 121             self.run_tst_program(program, [1, 2, 3])
 122
 123     def test_addis(self):
 124         lst = ["addi 1, 0, 0x0FFF",
 125                "addis 1, 1, 0x0F"
 126                ]
 127         with Program(lst) as program:
 128             self.run_tst_program(program, [1])
 129
 130     @unittest.skip("broken")
 131     def test_mulli(self):
 132         lst = ["addi 1, 0, 3",
 133                "mulli 1, 1, 2"
 134                ]
 135         with Program(lst) as program:
 136             self.run_tst_program(program, [1])
 137
 138     def run_tst_program(self, prog, reglist):
 139         simulator = self.run_tst(prog)
 140         prog.reset()
 141         with run_program(prog) as q:
 142             self.qemu_register_compare(simulator, q, reglist)
 143         print(simulator.gpr.dump())
 144
 145
 146     def qemu_register_compare(self, simulator, qemu, regs):
 147         for reg in regs:
 148             qemu_val = qemu.get_register(reg)
 149             sim_val = simulator.gpr(reg).value
 150             self.assertEqual(qemu_val, sim_val)
 151
 152
 153 if __name__ == "__main__":
 154     unittest.main()