3afb0e04cafdeaa067ff53a5811a13e6811f3b87
1 """Simple GPIO peripheral on wishbone
3 This is an extremely simple GPIO peripheral intended for use in XICS
4 testing, however it could also be used as an actual GPIO peripheral
6 Modified for use with pinmux, will probably change the class name later.
8 from random
import randint
9 from math
import ceil
, floor
10 from nmigen
import Elaboratable
, Module
, Signal
, Record
, Array
, Cat
11 from nmigen
.hdl
.rec
import Layout
12 from nmigen
.utils
import log2_int
13 from nmigen
.cli
import rtlil
14 from soc
.minerva
.wishbone
import make_wb_layout
15 from nmutil
.util
import wrap
16 from soc
.bus
.test
.wb_rw
import wb_read
, wb_write
18 from nmutil
.gtkw
import write_gtkw
22 from nmigen
.sim
.cxxsim
import Simulator
, Settle
24 from nmigen
.sim
import Simulator
, Settle
26 io_layout
= (("i", 1),
31 class IOMuxBlockSingle(Elaboratable
):
34 print("1-bit IO Mux Block")
36 self
.bank
= Signal(log2_int(self
.n_banks
))
39 for i
in range(self
.n_banks
):
40 temp_str
= "bank{}".format(i
)
41 temp
.append(Record(name
=temp_str
, layout
=io_layout
))
42 self
.bank_ports
= Array(temp
)
44 self
.out_port
= Record(name
="IO", layout
=io_layout
)
46 #self.b0 = Record(name="b0", layout=io_layout)
47 #self.b1 = Record(name="b1", layout=io_layout)
49 def elaborate(self
, platform
):
51 comb
, sync
= m
.d
.comb
, m
.d
.sync
54 bank_ports
= self
.bank_ports
57 out_port
= self
.out_port
59 sync
+= out_port
.o
.eq(bank_ports
[0].o
)
60 sync
+= out_port
.oe
.eq(bank_ports
[0].oe
)
61 sync
+= bank_ports
[0].i
.eq(out_port
.i
)
63 # Connect IO Pad output port to one of the peripheral IOs
64 # Connect peripheral inputs to the IO pad input
66 bank_range
= range(self
.n_banks
)
74 with m
.Case(BANK0_WB
):
75 self
.connect_bank_to_io(sync
, BANK0_WB
)
76 with m
.Case(BANK1_P1
):
77 self
.connect_bank_to_io(sync
, BANK1_P1
)
78 with m
.Case(BANK2_P2
):
79 self
.connect_bank_to_io(sync
, BANK2_P2
)
80 with m
.Case(BANK3_P3
):
81 self
.connect_bank_to_io(sync
, BANK3_P3
)
84 def connect_bank_to_io(self
, domain
, bank_arg
):
85 domain
+= self
.out_port
.o
.eq(self
.bank_ports
[bank_arg
].o
)
86 domain
+= self
.out_port
.oe
.eq(self
.bank_ports
[bank_arg
].oe
)
87 domain
+= self
.bank_ports
[bank_arg
].i
.eq(self
.out_port
.i
)
89 temp_list
= list(range(self
.n_banks
))
90 temp_list
.pop(temp_list
.index(bank_arg
))
91 print("Banks with input hardwired to 0: {}".format(temp_list
))
92 for j
in range(len(temp_list
)):
93 unused_bank
= temp_list
[j
]
94 domain
+= self
.bank_ports
[unused_bank
].i
.eq(0)
97 """ Get member signals for Verilog form. """
98 for field
in self
.out_port
.fields
.values():
100 for bank
in range(len(self
.bank_ports
)):
101 for field
in self
.bank_ports
[bank
].fields
.values():
108 def gen_gtkw_doc(module_name
, n_banks
, filename
):
109 # GTKWave doc generation
112 'in': {'color': 'orange'},
113 'out': {'color': 'yellow'},
114 'debug': {'module': 'top', 'color': 'red'}
117 # Create a trace list, each block expected to be a tuple()
119 for bank
in range(0, n_banks
):
120 temp_traces
= ('Bank{}'.format(bank
), [
121 ('bank{}__i'.format(bank
), 'in'),
122 ('bank{}__o'.format(bank
), 'out'),
123 ('bank{}__oe'.format(bank
), 'out')
125 traces
.append(temp_traces
)
127 temp_traces
= ('Misc', [
131 traces
.append(temp_traces
)
132 temp_traces
= ('IO port to pad', [
137 traces
.append(temp_traces
)
140 write_gtkw(filename
+".gtkw", filename
+".vcd", traces
, style
,
144 filename
= "test_pinmux" # Doesn't include extension
145 dut
= IOMuxBlockSingle()
146 vl
= rtlil
.convert(dut
, ports
=dut
.ports())
147 with
open(filename
+".il", "w") as f
:
151 m
.submodules
.pinmux
= dut
156 sim
.add_sync_process(wrap(test_iomux(dut
)))
157 sim_writer
= sim
.write_vcd(filename
+".vcd")
161 gen_gtkw_doc("top.pinmux", dut
.n_banks
, filename
)
164 print("------START----------------------")
165 #print(dir(dut.bank_ports[0]))
166 #print(dut.bank_ports[0].fields)
168 # TODO: turn into methods
169 yield dut
.bank_ports
[0].o
.eq(1)
172 yield dut
.bank_ports
[0].o
.eq(1)
174 yield dut
.bank_ports
[1].o
.eq(1)
176 yield dut
.bank_ports
[0].oe
.eq(1)
181 yield dut
.bank_ports
[0].o
.eq(0)
183 yield dut
.bank_ports
[1].o
.eq(0)
185 yield dut
.bank_ports
[1].oe
.eq(1)
192 yield dut
.bank_ports
[1].o
.eq(1)
194 yield dut
.bank_ports
[2].o
.eq(1)
196 yield dut
.bank_ports
[1].oe
.eq(1)
201 yield dut
.bank_ports
[1].o
.eq(0)
203 yield dut
.bank_ports
[2].o
.eq(0)
205 yield dut
.bank_ports
[2].oe
.eq(1)
210 print("Finished the 1-bit IO mux block test!")
212 if __name__
== '__main__':