25c3b5ac14260d9b9ee5a15dee8d1b13f4f93bec
1 """Simple GPIO peripheral on wishbone
3 This is an extremely simple GPIO peripheral intended for use in XICS
4 testing, however it could also be used as an actual GPIO peripheral
6 Modified for use with pinmux, will probably change the class name later.
8 from random
import randint
9 from math
import ceil
, floor
10 from nmigen
import Elaboratable
, Module
, Signal
, Record
, Array
, Cat
11 from nmigen
.hdl
.rec
import Layout
12 from nmigen
.utils
import log2_int
13 from nmigen
.cli
import rtlil
14 from soc
.minerva
.wishbone
import make_wb_layout
15 from nmutil
.util
import wrap
16 from soc
.bus
.test
.wb_rw
import wb_read
, wb_write
18 from nmutil
.gtkw
import write_gtkw
22 from nmigen
.sim
.cxxsim
import Simulator
, Settle
24 from nmigen
.sim
import Simulator
, Settle
26 # Layout of 8-bit configuration word:
27 # bank[2:0] i/o | pden puen ien oe
28 NUMBANKBITS
= 3 # max 3 bits, only supporting 4 banks (0-3)
29 csrbus_layout
= (("oe", 1),
37 gpio_layout
= (("i", 1),
45 class SimpleGPIO(Elaboratable
):
47 def __init__(self
, wordsize
=4, n_gpio
=16):
48 print("SimpleGPIO: WB Data # of bytes: {0}, # of GPIOs: {1}"
49 .format(wordsize
, n_gpio
))
50 self
.wordsize
= wordsize
56 spec
.reg_wid
= wordsize
*8 # 32
57 self
.bus
= Record(make_wb_layout(spec
), name
="gpio_wb")
59 print("CSRBUS layout: ", csrbus_layout
)
60 # create array - probably a cleaner way to do this...
62 for i
in range(self
.wordsize
):
63 temp_str
= "word{}".format(i
)
64 temp
.append(Record(name
=temp_str
, layout
=csrbus_layout
))
65 self
.multicsrbus
= Array(temp
)
68 for i
in range(self
.n_gpio
):
69 temp_str
= "gpio{}".format(i
)
70 temp
.append(Record(name
=temp_str
, layout
=gpio_layout
))
71 self
.gpio_ports
= Array(temp
)
73 def elaborate(self
, platform
):
75 comb
, sync
= m
.d
.comb
, m
.d
.sync
78 wb_rd_data
= bus
.dat_r
79 wb_wr_data
= bus
.dat_w
82 gpio_ports
= self
.gpio_ports
83 multi
= self
.multicsrbus
87 row_start
= Signal(log2_int(self
.n_gpio
))
88 # Flag for indicating rd/wr transactions
89 new_transaction
= Signal(1)
92 #print("gpio_addr: ", type(gpio_addr))
94 # One address used to configure CSR, set output, read input
95 with m
.If(bus
.cyc
& bus
.stb
):
96 comb
+= wb_ack
.eq(1) # always ack
98 sync
+= row_start
.eq(bus
.adr
* self
.wordsize
)
99 sync
+= new_transaction
.eq(1)
100 with m
.If(bus
.we
): # write
102 for byte
in range(0, self
.wordsize
):
103 sync
+= multi
[byte
].eq(wb_wr_data
[byte
*8:8+byte
*8])
104 with m
.Else(): # read
105 # Concatinate the GPIO configs that are on the same "row" or
108 for i
in range(0, self
.wordsize
):
109 multi_cat
.append(multi
[i
])
110 comb
+= wb_rd_data
.eq(Cat(multi_cat
))
112 sync
+= new_transaction
.eq(0)
113 # Update the state of "io" while no WB transactions
114 for byte
in range(0, self
.wordsize
):
115 with m
.If(gpio_ports
[row_start
+byte
].oe
):
116 sync
+= multi
[byte
].io
.eq(gpio_ports
[row_start
+byte
].o
)
118 sync
+= multi
[byte
].io
.eq(gpio_ports
[row_start
+byte
].i
)
119 # Only update GPIOs config if a new transaction happened last cycle
120 # (read or write). Always lags from multi csrbus by 1 clk cycle, most
121 # sane way I could think of while using Record().
122 with m
.If(new_transaction
):
123 for byte
in range(0, self
.wordsize
):
124 sync
+= gpio_ports
[row_start
+byte
].oe
.eq(multi
[byte
].oe
)
125 sync
+= gpio_ports
[row_start
+byte
].puen
.eq(multi
[byte
].puen
)
126 sync
+= gpio_ports
[row_start
+byte
].pden
.eq(multi
[byte
].pden
)
127 # Check to prevent output being set if GPIO configured as input
128 # TODO: No checking is done if ie/oe high together
129 with m
.If(gpio_ports
[row_start
+byte
].oe
):
130 sync
+= gpio_ports
[row_start
+byte
].o
.eq(multi
[byte
].io
)
131 sync
+= gpio_ports
[row_start
+byte
].bank
.eq(multi
[byte
].bank
)
135 for field
in self
.bus
.fields
.values():
142 def gpio_test_in_pattern(dut
, pattern
):
143 num_gpios
= len(dut
.gpio_ports
)
144 print("Test pattern:")
146 for pat
in range(0, len(pattern
)):
147 for gpio
in range(0, num_gpios
):
148 yield from gpio_set_in_pad(dut
, gpio
, pattern
[pat
])
150 temp
= yield from gpio_rd_input(dut
, gpio
)
151 print("Pattern: {0}, Reading {1}".format(pattern
[pat
], temp
))
152 assert (temp
== pattern
[pat
])
154 if pat
== len(pattern
):
157 def test_gpio_single(dut
, gpio
, use_random
=True):
164 bank
= randint(0, (2**NUMBANKBITS
)-1)
165 print("Random bank select: {0:b}".format(bank
))
167 bank
= 3 # not special, chose for testing
169 gpio_csr
= yield from gpio_config(dut
, gpio
, oe
, ie
, puen
, pden
, output
,
173 gpio_csr
= yield from gpio_config(dut
, gpio
, oe
, ie
, puen
, pden
, output
,
176 # Shadow reg container class
177 class GPIOConfigReg():
178 def __init__(self
, shift_dict
):
179 self
.shift_dict
= shift_dict
188 def set(self
, oe
=0, ie
=0, puen
=0, pden
=0, io
=0, bank
=0):
195 self
.pack() # Produce packed byte for sending
197 def set_out(self
, outval
):
199 self
.pack() # Produce packed byte for sending
201 # Take config parameters of specified GPIOs, and combine them to produce
202 # bytes for sending via WB bus
204 self
.packed
= ((self
.oe
<< self
.shift_dict
['oe'])
205 |
(self
.ie
<< self
.shift_dict
['ie'])
206 |
(self
.puen
<< self
.shift_dict
['puen'])
207 |
(self
.pden
<< self
.shift_dict
['pden'])
208 |
(self
.io
<< self
.shift_dict
['io'])
209 |
(self
.bank
<< self
.shift_dict
['bank']))
211 #print("GPIO Packed CSR: {0:x}".format(self.packed))
213 # Object for storing each gpio's config state
216 def __init__(self
, dut
, layout
):
218 # arrangement of config bits making up csr word
219 self
.csr_layout
= layout
220 self
.shift_dict
= self
._create
_shift
_dict
()
221 self
.n_gpios
= len(self
.dut
.gpio_ports
)
223 # Since GPIO HDL block already has wordsize parameter, use directly
224 # Alternatively, can derive from WB data r/w buses (div by 8 for bytes)
225 #self.wordsize = len(self.dut.gpio_wb__dat_w) / 8
226 self
.wordsize
= self
.dut
.wordsize
227 self
.n_rows
= ceil(self
.n_gpios
/ self
.wordsize
)
229 for i
in range(self
.n_gpios
):
230 self
.shadow_csr
.append(GPIOConfigReg(self
.shift_dict
))
232 def print_info(self
):
234 print("GPIO Block Info:")
235 print("Number of GPIOs: {}".format(self
.n_gpios
))
236 print("WB Data bus width (in bytes): {}".format(self
.wordsize
))
237 print("Number of rows: {}".format(self
.n_rows
))
240 # The shifting of control bits in the configuration word is dependent on the
241 # defined layout. To prevent maintaining the shift constants in a separate
242 # location, the same layout is used to generate a dictionary of bit shifts
243 # with which the configuration word can be produced!
244 def _create_shift_dict(self
):
247 for i
in range(0, len(self
.csr_layout
)):
248 shift_dict
[self
.csr_layout
[i
][0]] = shift
249 shift
+= self
.csr_layout
[i
][1]
253 def _parse_gpio_arg(self
, gpio_str
):
254 # TODO: No input checking!
255 print("Given GPIO/range string: {}".format(gpio_str
))
256 if gpio_str
== "all":
259 elif '-' in gpio_str
:
260 start
, end
= gpio_str
.split('-')
263 if (end
< start
) or (end
> self
.n_gpios
):
264 raise Exception("Second GPIO must be higher than first and"
265 + " must be lower or equal to last available GPIO.")
267 start
= int(gpio_str
)
268 if start
>= self
.n_gpios
:
269 raise Exception("GPIO must be less/equal to last GPIO.")
271 print("Parsed GPIOs {0} until {1}".format(start
, end
))
274 # Take a combined word and update shadow reg's
275 # TODO: convert hard-coded sizes to use the csrbus_layout (or dict?)
276 def update_single_shadow(self
, csr_byte
, gpio
):
277 oe
= (csr_byte
>> self
.shift_dict
['oe']) & 0x1
278 ie
= (csr_byte
>> self
.shift_dict
['ie']) & 0x1
279 puen
= (csr_byte
>> self
.shift_dict
['puen']) & 0x1
280 pden
= (csr_byte
>> self
.shift_dict
['pden']) & 0x1
281 io
= (csr_byte
>> self
.shift_dict
['io']) & 0x1
282 bank
= (csr_byte
>> self
.shift_dict
['bank']) & 0x3
284 print("csr={0:x} | oe={1}, ie={2}, puen={3}, pden={4}, io={5}, bank={6}"
285 .format(csr_byte
, oe
, ie
, puen
, pden
, io
, bank
))
287 self
.shadow_csr
[gpio
].set(oe
, ie
, puen
, pden
, io
, bank
)
288 return oe
, ie
, puen
, pden
, io
, bank
290 def rd_csr(self
, row_start
):
291 row_word
= yield from wb_read(self
.dut
.bus
, row_start
)
292 print("Returned CSR: {0:x}".format(row_word
))
295 # Update a single row of configuration registers
296 def wr_row(self
, row_addr
, check
=False):
297 curr_gpio
= row_addr
* self
.wordsize
299 for byte
in range(0, self
.wordsize
):
300 if curr_gpio
>= self
.n_gpios
:
302 config_word
+= self
.shadow_csr
[curr_gpio
].packed
<< (8 * byte
)
303 #print("Reading GPIO{} shadow reg".format(curr_gpio))
305 print("Writing shadow CSRs val {0:x} to row addr {1:x}"
306 .format(config_word
, row_addr
))
307 yield from wb_write(self
.dut
.bus
, row_addr
, config_word
)
308 yield # Allow one clk cycle to propagate
311 read_word
= yield from self
.rd_row(row_addr
)
312 assert config_word
== read_word
314 # Read a single address row of GPIO CSRs, and update shadow
315 def rd_row(self
, row_addr
):
316 read_word
= yield from self
.rd_csr(row_addr
)
317 curr_gpio
= row_addr
* self
.wordsize
319 for byte
in range(0, self
.wordsize
):
320 if curr_gpio
>= self
.n_gpios
:
322 single_csr
= (read_word
>> (8 * byte
)) & 0xFF
323 #print("Updating GPIO{0} shadow reg to {1:x}"
324 # .format(curr_gpio, single_csr))
325 self
.update_single_shadow(single_csr
, curr_gpio
)
329 # Write all shadow registers to GPIO block
330 def wr_all(self
, check
=False):
331 for row
in range(0, self
.n_rows
):
332 yield from self
.wr_row(row
, check
)
334 # Read all GPIO block row addresses and update shadow reg's
335 def rd_all(self
, check
=False):
336 for row
in range(0, self
.n_rows
):
337 yield from self
.rd_row(row
, check
)
339 def config(self
, gpio_str
, oe
, ie
, puen
, pden
, outval
, bank
, check
=False):
340 start
, end
= self
._parse
_gpio
_arg
(gpio_str
)
341 # Update the shadow configuration
342 for gpio
in range(start
, end
):
343 # print(oe, ie, puen, pden, outval, bank)
344 self
.shadow_csr
[gpio
].set(oe
, ie
, puen
, pden
, outval
, bank
)
345 # TODO: only update the required rows?
346 yield from self
.wr_all()
348 # Set/Clear the output bit for single or group of GPIOs
349 def set_out(self
, gpio_str
, outval
):
350 start
, end
= self
._parse
_gpio
_arg
(gpio_str
)
351 for gpio
in range(start
, end
):
352 self
.shadow_csr
[gpio
].set_out(outval
)
355 print("Setting GPIO{0} output to {1}".format(start
, outval
))
357 print("Setting GPIOs {0}-{1} output to {2}"
358 .format(start
, end
-1, outval
))
360 yield from self
.wr_all()
362 def rd_input(self
, gpio_str
): # REWORK
363 start
, end
= self
._parse
_gpio
_arg
(gpio_str
)
365 # Too difficult to think about, just read all configs
366 #start_row = floor(start / self.wordsize)
367 # Hack because end corresponds to range limit, but maybe on same row
369 #end_row = floor( (end-1) / self.wordsize) + 1
370 read_data
= [0] * self
.n_rows
371 for row
in range(0, self
.n_rows
):
372 read_data
[row
] = yield from self
.rd_row(row
)
374 num_to_read
= (end
- start
)
375 read_in
= [0] * num_to_read
377 for i
in range(0, num_to_read
):
378 read_in
[i
] = self
.shadow_csr
[curr_gpio
].io
381 print("GPIOs {0} until {1}, i={2}".format(start
, end
, read_in
))
384 # TODO: There's probably a cleaner way to clear the bit...
385 def sim_set_in_pad(self
, gpio_str
, in_val
):
386 start
, end
= self
._parse
_gpio
_arg
(gpio_str
)
387 for gpio
in range(start
, end
):
388 old_in_val
= yield self
.dut
.gpio_ports
[gpio
].i
390 print("GPIO{0} Previous i: {1:b} | New i: {2:b}"
391 .format(gpio
, old_in_val
, in_val
))
392 yield self
.dut
.gpio_ports
[gpio
].i
.eq(in_val
)
393 yield # Allow one clk cycle to propagate
396 shadow_csr
= [0] * self
.n_gpios
397 for gpio
in range(0, self
.n_gpios
):
398 shadow_csr
[gpio
] = self
.shadow_csr
[gpio
].packed
401 for reg
in shadow_csr
:
402 hex_str
+= " "+hex(reg
)
403 print("Shadow reg's: ", hex_str
)
408 def sim_gpio(dut
, use_random
=True):
410 #print(dir(dut.gpio_ports))
411 #print(len(dut.gpio_ports))
413 gpios
= GPIOManager(dut
, csrbus_layout
)
415 # TODO: not working yet
417 #for i in range(0, (num_gpios * 2)):
418 # test_pattern.append(randint(0,1))
419 #yield from gpio_test_in_pattern(dut, test_pattern)
421 #yield from gpio_config(dut, start_gpio, oe, ie, puen, pden, outval, bank, end_gpio, check=False, wordsize=4)
422 #reg_val = 0xC56271A2
423 #reg_val = 0xFFFFFFFF
424 #yield from reg_write(dut, 0, reg_val)
425 #yield from reg_write(dut, 0, reg_val)
428 #csr_val = yield from wb_read(dut.bus, 0)
429 #print("CSR Val: {0:x}".format(csr_val))
430 print("Finished the simple GPIO block test!")
432 def gen_gtkw_doc(n_gpios
, wordsize
, filename
):
433 # GTKWave doc generation
434 wb_data_width
= wordsize
*8
435 n_rows
= ceil(n_gpios
/wordsize
)
438 'in': {'color': 'orange'},
439 'out': {'color': 'yellow'},
440 'debug': {'module': 'top', 'color': 'red'}
443 # Create a trace list, each block expected to be a tuple()
445 wb_traces
= ('Wishbone Bus', [
446 ('gpio_wb__cyc', 'in'),
447 ('gpio_wb__stb', 'in'),
448 ('gpio_wb__we', 'in'),
449 ('gpio_wb__adr[27:0]', 'in'),
450 ('gpio_wb__dat_w[{}:0]'.format(wb_data_width
-1), 'in'),
451 ('gpio_wb__dat_r[{}:0]'.format(wb_data_width
-1), 'out'),
452 ('gpio_wb__ack', 'out'),
454 traces
.append(wb_traces
)
456 gpio_internal_traces
= ('Internal', [
462 traces
.append(gpio_internal_traces
)
464 traces
.append({'comment': 'Multi-byte GPIO config bus'})
465 for word
in range(0, wordsize
):
466 prefix
= "word{}__".format(word
)
469 single_word
.append('Word{}'.format(word
))
470 word_signals
.append((prefix
+'bank[{}:0]'.format(NUMBANKBITS
-1)))
471 word_signals
.append((prefix
+'ie'))
472 word_signals
.append((prefix
+'io'))
473 word_signals
.append((prefix
+'oe'))
474 word_signals
.append((prefix
+'pden'))
475 word_signals
.append((prefix
+'puen'))
476 single_word
.append(word_signals
)
477 traces
.append(tuple(single_word
))
479 for gpio
in range(0, n_gpios
):
480 prefix
= "gpio{}__".format(gpio
)
483 single_gpio
.append('GPIO{} Port'.format(gpio
))
484 gpio_signals
.append((prefix
+'bank[{}:0]'.format(NUMBANKBITS
-1), 'out'))
485 gpio_signals
.append( (prefix
+'i', 'in') )
486 gpio_signals
.append( (prefix
+'o', 'out') )
487 gpio_signals
.append( (prefix
+'oe', 'out') )
488 gpio_signals
.append( (prefix
+'pden', 'out') )
489 gpio_signals
.append( (prefix
+'puen', 'out') )
490 single_gpio
.append(gpio_signals
)
491 traces
.append(tuple(single_gpio
))
495 write_gtkw(filename
+".gtkw", filename
+".vcd", traces
, style
,
496 module
="top.xics_icp")
499 filename
= "test_gpio" # Doesn't include extension
501 wordsize
= 4 # Number of bytes in the WB data word
502 dut
= SimpleGPIO(wordsize
, n_gpios
)
503 vl
= rtlil
.convert(dut
, ports
=dut
.ports())
504 with
open(filename
+".il", "w") as f
:
508 m
.submodules
.xics_icp
= dut
513 #sim.add_sync_process(wrap(sim_gpio(dut, use_random=False)))
514 sim
.add_sync_process(wrap(test_gpioman(dut
)))
515 sim_writer
= sim
.write_vcd(filename
+".vcd")
519 gen_gtkw_doc(n_gpios
, wordsize
, filename
)
521 def test_gpioman(dut
):
522 print("------START----------------------")
523 gpios
= GPIOManager(dut
, csrbus_layout
)
525 #gpios._parse_gpio_arg("all")
526 #gpios._parse_gpio_arg("0")
527 gpios
._parse
_gpio
_arg
("1-3")
528 #gpios._parse_gpio_arg("20")
536 yield from gpios
.config("0-3", oe
=1, ie
=0, puen
=0, pden
=1, outval
=0, bank
=2)
538 yield from gpios
.config("4-7", oe
=0, ie
=1, puen
=0, pden
=1, outval
=0, bank
=2)
539 yield from gpios
.set_out("0-3", outval
=1)
541 #yield from gpios.rd_all()
542 yield from gpios
.sim_set_in_pad("4-7", 1)
543 print("----------------------------")
544 yield from gpios
.rd_input("4-7")
548 if __name__
== '__main__':