9b5ec08ad877118f6df381b7b7a6bd8e52b8f439
1 """Simple GPIO peripheral on wishbone
3 This is an extremely simple GPIO peripheral intended for use in XICS
4 testing, however it could also be used as an actual GPIO peripheral
6 Modified for use with pinmux, will probably change the class name later.
8 from random
import randint
9 from nmigen
import Elaboratable
, Module
, Signal
, Record
, Array
10 from nmigen
.hdl
.rec
import Layout
11 from nmigen
.utils
import log2_int
12 from nmigen
.cli
import rtlil
13 from soc
.minerva
.wishbone
import make_wb_layout
14 from nmutil
.util
import wrap
15 from soc
.bus
.test
.wb_rw
import wb_read
, wb_write
19 from nmigen
.sim
.cxxsim
import Simulator
, Settle
21 from nmigen
.sim
import Simulator
, Settle
23 # Layout of 8-bit configuration word:
24 # bank_select[2:0] i/o | pden puen ien oe
31 NUMBANKBITS
= 3 # only supporting 8 banks (0-7)
34 WORDSIZE
= 8 # in bytes
36 class CSRLayout(Layout
):
41 ("puen", unsigned(1)),
42 ("pden", unsigned(1)),
44 ("bank_sel", unsigned(NUMBANKBITS
))
49 super().__init
__(CSRLayout
)
51 class SimpleGPIO(Elaboratable
):
53 def __init__(self
, n_gpio
=16):
60 self
.bus
= Record(make_wb_layout(spec
), name
="gpio_wb")
61 self
.bank_sel
= Array([Signal(NUMBANKBITS
) for _
in range(n_gpio
)])
62 self
.gpio_o
= Signal(n_gpio
)
63 self
.gpio_oe
= Signal(n_gpio
)
64 self
.gpio_i
= Signal(n_gpio
)
65 self
.gpio_ie
= Signal(n_gpio
)
66 self
.pden
= Signal(n_gpio
)
67 self
.puen
= Signal(n_gpio
)
68 self
.csrbus
= CSRBus()
70 def elaborate(self
, platform
):
72 comb
, sync
= m
.d
.comb
, m
.d
.sync
75 wb_rd_data
= bus
.dat_r
76 wb_wr_data
= bus
.dat_w
79 bank_sel
= self
.bank_sel
81 gpio_oe
= self
.gpio_oe
83 gpio_ie
= self
.gpio_ie
90 gpio_addr
= Signal(log2_int(self
.n_gpio
))
91 gpio_o_list
= Array(list(gpio_o
))
94 gpio_oe_list
= Array(list(gpio_oe
))
95 gpio_i_list
= Array(list(gpio_i
))
96 gpio_ie_list
= Array(list(gpio_ie
))
97 pden_list
= Array(list(pden
))
98 puen_list
= Array(list(puen
))
101 #print("gpio_addr: ", type(gpio_addr))
102 #print("gpio_o_list: ", type(gpio_o_list))
103 #print("bank_sel: ", type(bank_sel))
105 # One address used to configure CSR, set output, read input
106 with m
.If(bus
.cyc
& bus
.stb
):
107 comb
+= wb_ack
.eq(1) # always ack
108 comb
+= gpio_addr
.eq(bus
.adr
)
109 with m
.If(bus
.we
): # write
111 sync
+= csrbus
.eq(wb_wr_data
)
112 sync
+= gpio_oe_list
[gpio_addr
].eq(csrbus
.oe
)
113 sync
+= gpio_ie_list
[gpio_addr
].eq(csrbus
.ie
)
114 # check GPIO is in output mode and NOT input (oe high, ie low)
115 with m
.If(csrbus
.oe
& (~csrbus
.ie
)):
116 sync
+= gpio_o_list
[gpio_addr
].eq(csrbus
.io
)
117 sync
+= puen_list
[gpio_addr
].eq(csrbus
.puen
)
118 sync
+= pden_list
[gpio_addr
].eq(csrbus
.pden
)
119 # TODO: clean up name
120 sync
+= bank_sel
[gpio_addr
].eq(csrbus
.bank_sel
)
121 with m
.Else(): # read
122 # Read the state of CSR bits
123 # Return state of input if ie
125 with m
.If(gpio_ie_list
[gpio_addr
] == 1):
126 comb
+= csrbus
.ie
.eq(gpio_i_list
[gpio_addr
])
127 comb
+= wb_rd_data
.eq(csrbus
)
128 #comb += wb_rd_data.eq((gpio_oe_list[gpio_addr] << OESHIFT)
129 # + (gpio_ie_list[gpio_addr] << IESHIFT)
130 # + (puen_list[gpio_addr] << PUSHIFT)
131 # + (pden_list[gpio_addr] << PDSHIFT)
132 # + (gpio_i_list[gpio_addr] << IOSHIFT)
133 # + (bank_sel[gpio_addr] << BANKSHIFT))
134 # Return state of out if oe
136 comb
+= wb_rd_data
.eq((gpio_oe_list
[gpio_addr
] << OESHIFT
)
137 + (gpio_ie_list
[gpio_addr
] << IESHIFT
)
138 + (puen_list
[gpio_addr
] << PUSHIFT
)
139 + (pden_list
[gpio_addr
] << PDSHIFT
)
140 + (gpio_o_list
[gpio_addr
] << IOSHIFT
)
141 + (bank_sel
[gpio_addr
] << BANKSHIFT
))
146 for field
in self
.bus
.fields
.values():
153 # TODO: probably make into class (or return state in a variable)
154 def gpio_configure(dut
, gpio
, oe
, ie
, puen
, pden
, outval
, bank_sel
):
155 csr_val
= ( (oe
<< OESHIFT
)
159 |
(bank_sel
<< BANKSHIFT
) )
160 print("Configuring CSR to {0:x}".format(csr_val
))
161 yield from wb_write(dut
.bus
, gpio
, csr_val
)
162 return csr_val
# return the config state
164 # TODO: Return the configuration states
165 def gpio_rd_csr(dut
, gpio
):
166 csr_val
= yield from wb_read(dut
.bus
, gpio
)
167 print("GPIO{0} | CSR: {1:x}".format(gpio
, csr_val
))
168 print("Output Enable: {0:b}".format((csr_val
>> OESHIFT
) & 1))
169 print("Input Enable: {0:b}".format((csr_val
>> IESHIFT
) & 1))
170 print("Pull-Up Enable: {0:b}".format((csr_val
>> PUSHIFT
) & 1))
171 print("Pull-Down Enable: {0:b}".format((csr_val
>> PDSHIFT
) & 1))
172 if ((csr_val
>> IESHIFT
) & 1):
173 print("Input: {0:b}".format((csr_val
>> IOSHIFT
) & 1))
175 print("Output: {0:b}".format((csr_val
>> IOSHIFT
) & 1))
176 print("Bank Select: {0:b}".format((csr_val
>> BANKSHIFT
) & 1))
177 # gpio_parse_csr(csr_val)
181 def gpio_rd_input(dut
, gpio
):
182 in_val
= yield from wb_read(dut
.bus
, gpio
)
183 in_val
= (in_val
>> IOSHIFT
) & 1
184 print("GPIO{0} | Input: {1:b}".format(gpio
, in_val
))
187 def gpio_set_out(dut
, gpio
, csr_val
, output
):
188 print("Setting GPIO{0} output to {1}".format(gpio
, output
))
189 yield from wb_write(dut
.bus
, gpio
, csr_val |
(output
<<IOSHIFT
))
191 # TODO: There's probably a cleaner way to clear the bit...
192 def gpio_set_in_pad(dut
, gpio
, in_val
):
193 old_in_val
= yield dut
.gpio_i
195 new_in_val
= old_in_val |
(in_val
<< gpio
)
197 temp
= (old_in_val
>> gpio
) & 1
200 new_in_val
= old_in_val
& mask
202 new_in_val
= old_in_val
203 print("Previous GPIO i: {0:b} | New GPIO i: {1:b}"
204 .format(old_in_val
, new_in_val
))
205 yield dut
.gpio_i
.eq(new_in_val
)
207 def gpio_test_in_pattern(dut
, pattern
):
208 num_gpios
= len(dut
.gpio_o
)
209 print("Test pattern:")
211 for pat
in range(0, len(pattern
)):
212 for gpio
in range(0, num_gpios
):
213 yield from gpio_set_in_pad(dut
, gpio
, pattern
[pat
])
215 temp
= yield from gpio_rd_input(dut
, gpio
)
216 print("Pattern: {0}, Reading {1}".format(pattern
[pat
], temp
))
217 assert (temp
== pattern
[pat
])
219 if pat
== len(pattern
):
223 def sim_gpio(dut
, use_random
=True):
226 num_gpios
= len(dut
.gpio_o
)
228 bank_sel
= randint(0, num_gpios
)
230 bank_sel
= 3 # not special, chose for testing
236 gpio_csr
= [0] * num_gpios
237 # Configure GPIOs for
238 for gpio
in range(0, num_gpios
):
239 gpio_csr
[gpio
] = yield from gpio_configure(dut
, gpio
, oe
, ie
, puen
,
240 pden
, output
, bank_sel
)
242 for gpio
in range(0, num_gpios
):
243 yield from gpio_set_out(dut
, gpio
, gpio_csr
[gpio
], 1)
246 for gpio
in range(0, num_gpios
):
247 yield from gpio_rd_csr(dut
, gpio
)
249 # TODO: not working yet
251 #for i in range(0, (num_gpios * 2)):
252 # test_pattern.append(randint(0,1))
253 #yield from gpio_test_in_pattern(dut, test_pattern)
255 print("Finished the simple GPIO block test!")
259 vl
= rtlil
.convert(dut
, ports
=dut
.ports())
260 with
open("test_gpio.il", "w") as f
:
264 m
.submodules
.xics_icp
= dut
269 sim
.add_sync_process(wrap(sim_gpio(dut
)))
270 sim_writer
= sim
.write_vcd('test_gpio.vcd')
275 if __name__
== '__main__':