src/spec/testing.py

   1 from UserDict import UserDict
   2
   3
   4 class Wire(object):
   5     """ a wire which can be hi, lo or tri-state
   6     """
   7
   8     def __init__(self, wires, name):
   9         self.wires = wires
  10         self.wires[name] = self
  11         self.name = name
  12         self.val = 'x'
  13
  14
  15 class TestPin(object):
  16     """ a test pin can be an output, input or in-out
  17         and it stores the state in an associated wire
  18     """
  19
  20
  21 class Wires(UserDict):
  22     """ a set of wires
  23     """
  24
  25     def __init__(self):
  26         UserDict.__init__(self)
  27
  28
  29 def dummytest(ps, output_dir, output_type):
  30     print ps, output_dir, output_type
  31     print dir(ps)
  32     print ps.fnspec
  33
  34     # basically we need to replicate the entirety of the
  35     # verilog module's inputs and outputs, so that we can
  36     # set inputs hi/lo and then test expected outputs hi/lo.
  37     # so, set up some wires by going through the interfaces
  38     w = Wires()