073ba0f641251ddd979d5001a13e6021383f7c5c
3 pinmux documented here https://libre-soc.org/docs/pinmux/
5 from nmigen
.build
.dsl
import Resource
, Subsignal
, Pins
6 from nmigen
.build
.plat
import TemplatedPlatform
7 from nmigen
.build
.res
import ResourceManager
, ResourceError
8 from nmigen
.hdl
.rec
import Layout
9 from nmigen
import Elaboratable
, Signal
, Module
, Instance
10 from collections
import OrderedDict
11 from jtag
import JTAG
, resiotypes
12 from copy
import deepcopy
13 from nmigen
.cli
import rtlil
16 # extra dependencies for jtag testing (?)
17 #from soc.bus.sram import SRAM
19 #from nmigen import Memory
20 from nmigen
.sim
import Simulator
, Delay
, Settle
, Tick
, Passive
22 from nmutil
.util
import wrap
24 #from soc.debug.jtagutils import (jtag_read_write_reg,
25 # jtag_srv, jtag_set_reset,
26 # jtag_set_ir, jtag_set_get_dr)
28 from c4m
.nmigen
.jtag
.tap
import TAP
, IOType
29 from c4m
.nmigen
.jtag
.bus
import Interface
as JTAGInterface
30 #from soc.debug.dmi import DMIInterface, DBGCore
31 #from soc.debug.test.dmi_sim import dmi_sim
32 #from soc.debug.test.jtagremote import JTAGServer, JTAGClient
33 from nmigen
.build
.res
import ResourceError
35 # Was thinking of using these functions, but skipped for simplicity for now
36 # XXX nope. the output from JSON file.
37 #from pinfunctions import (i2s, lpc, emmc, sdmmc, mspi, mquadspi, spi,
38 # quadspi, i2c, mi2c, jtag, uart, uartfull, rgbttl, ulpi, rgmii, flexbus1,
39 # flexbus2, sdram1, sdram2, sdram3, vss, vdd, sys, eint, pwm, gpio)
41 # File for stage 1 pinmux tested proposed by Luke,
42 # https://bugs.libre-soc.org/show_bug.cgi?id=50#c10
46 # sigh this needs to come from pinmux.
49 gpios
.append("%d*" % i
)
50 return {'uart': ['tx+', 'rx-'],
52 #'jtag': ['tms-', 'tdi-', 'tdo+', 'tck+'],
53 'i2c': ['sda*', 'scl+']}
56 a function is needed which turns the results of dummy_pinset()
59 [UARTResource("uart", 0, tx=..., rx=..),
60 I2CResource("i2c", 0, scl=..., sda=...),
61 Resource("gpio", 0, Subsignal("i"...), Subsignal("o"...)
62 Resource("gpio", 1, Subsignal("i"...), Subsignal("o"...)
68 def create_resources(pinset
):
70 for periph
, pins
in pinset
.items():
73 #print("I2C required!")
74 resources
.append(I2CResource('i2c', 0, sda
='sda', scl
='scl'))
75 elif periph
== 'uart':
76 #print("UART required!")
77 resources
.append(UARTResource('uart', 0, tx
='tx', rx
='rx'))
78 elif periph
== 'gpio':
79 #print("GPIO required!")
80 print ("GPIO is defined as '*' type, meaning i, o and oe needed")
83 pname
= "gpio"+pin
[:-1] # strip "*" on end
84 # urrrr... tristsate and io assume a single pin which is
85 # of course exactly what we don't want in an ASIC: we want
86 # *all three* pins but the damn port is not outputted
87 # as a triplet, it's a single Record named "io". sigh.
88 # therefore the only way to get a triplet of i/o/oe
89 # is to *actually* create explicit triple pins
90 # XXX ARRRGH, doesn't work
91 #pad = Subsignal("io",
92 # Pins("%s_i %s_o %s_oe" % (pname, pname, pname),
93 # dir="io", assert_width=3))
94 #ios.append(Resource(pname, 0, pad))
96 pads
.append(Subsignal("i",
97 Pins(pname
+"_i", dir="i", assert_width
=1)))
98 pads
.append(Subsignal("o",
99 Pins(pname
+"_o", dir="o", assert_width
=1)))
100 pads
.append(Subsignal("oe",
101 Pins(pname
+"_oe", dir="o", assert_width
=1)))
102 ios
.append(Resource
.family(pname
, 0, default_name
=pname
,
104 resources
.append(Resource
.family(periph
, 0, default_name
="gpio",
107 # add clock and reset
108 clk
= Resource("clk", 0, Pins("sys_clk", dir="i"))
109 rst
= Resource("rst", 0, Pins("sys_rst", dir="i"))
110 resources
.append(clk
)
111 resources
.append(rst
)
115 def JTAGResource(*args
):
117 io
.append(Subsignal("tms", Pins("tms", dir="i", assert_width
=1)))
118 io
.append(Subsignal("tdi", Pins("tdi", dir="i", assert_width
=1)))
119 io
.append(Subsignal("tck", Pins("tck", dir="i", assert_width
=1)))
120 io
.append(Subsignal("tdo", Pins("tdo", dir="o", assert_width
=1)))
121 return Resource
.family(*args
, default_name
="jtag", ios
=io
)
123 def UARTResource(*args
, rx
, tx
):
125 io
.append(Subsignal("rx", Pins(rx
, dir="i", assert_width
=1)))
126 io
.append(Subsignal("tx", Pins(tx
, dir="o", assert_width
=1)))
127 return Resource
.family(*args
, default_name
="uart", ios
=io
)
130 def I2CResource(*args
, scl
, sda
):
133 pads
.append(Subsignal("i", Pins(sda
+"_i", dir="i", assert_width
=1)))
134 pads
.append(Subsignal("o", Pins(sda
+"_o", dir="o", assert_width
=1)))
135 pads
.append(Subsignal("oe", Pins(sda
+"_oe", dir="o", assert_width
=1)))
136 ios
.append(Resource
.family(sda
, 0, default_name
=sda
, ios
=pads
))
138 pads
.append(Subsignal("i", Pins(scl
+"_i", dir="i", assert_width
=1)))
139 pads
.append(Subsignal("o", Pins(scl
+"_o", dir="o", assert_width
=1)))
140 pads
.append(Subsignal("oe", Pins(scl
+"_oe", dir="o", assert_width
=1)))
141 ios
.append(Resource
.family(scl
, 0, default_name
=scl
, ios
=pads
))
142 return Resource
.family(*args
, default_name
="i2c", ios
=ios
)
145 # top-level demo module.
146 class Blinker(Elaboratable
):
147 def __init__(self
, pinset
, resources
, no_jtag_connect
=False):
148 self
.no_jtag_connect
= no_jtag_connect
149 self
.jtag
= JTAG({}, "sync", resources
=resources
)
150 #memory = Memory(width=32, depth=16)
151 #self.sram = SRAM(memory=memory, bus=self.jtag.wb)
153 def elaborate(self
, platform
):
154 jtag_resources
= self
.jtag
.pad_mgr
.resources
156 m
.submodules
.jtag
= self
.jtag
157 #m.submodules.sram = self.sram
160 #m.d.sync += count.eq(count+1)
161 print ("resources", platform
, jtag_resources
.items())
162 gpio
= self
.jtag
.request('gpio')
163 print (gpio
, gpio
.layout
, gpio
.fields
)
164 # get the GPIO bank, mess about with some of the pins
165 #m.d.comb += gpio.gpio0.o.eq(1)
166 #m.d.comb += gpio.gpio1.o.eq(gpio.gpio2.i)
167 #m.d.comb += gpio.gpio1.oe.eq(count[4])
168 #m.d.sync += count[0].eq(gpio.gpio1.i)
171 gpio_i_ro
= Signal(num_gpios
)
172 gpio_o_test
= Signal(num_gpios
)
173 gpio_oe_test
= Signal(num_gpios
)
175 # Create a read-only copy of core-side GPIO input signals
176 # for Simulation asserts
177 m
.d
.comb
+= gpio_i_ro
[0].eq(gpio
.gpio0
.i
)
178 m
.d
.comb
+= gpio_i_ro
[1].eq(gpio
.gpio1
.i
)
179 m
.d
.comb
+= gpio_i_ro
[2].eq(gpio
.gpio2
.i
)
180 m
.d
.comb
+= gpio_i_ro
[3].eq(gpio
.gpio3
.i
)
182 # Wire up the output signal of each gpio by XOR'ing each bit of
183 # gpio_o_test with gpio's input
184 # Wire up each bit of gpio_oe_test signal to oe signal of each gpio.
185 # Turn into a loop at some point, probably a way without
187 m
.d
.comb
+= gpio
.gpio0
.o
.eq(gpio_o_test
[0] ^ gpio
.gpio0
.i
)
188 m
.d
.comb
+= gpio
.gpio1
.o
.eq(gpio_o_test
[1] ^ gpio
.gpio1
.i
)
189 m
.d
.comb
+= gpio
.gpio2
.o
.eq(gpio_o_test
[2] ^ gpio
.gpio2
.i
)
190 m
.d
.comb
+= gpio
.gpio3
.o
.eq(gpio_o_test
[3] ^ gpio
.gpio3
.i
)
192 m
.d
.comb
+= gpio
.gpio0
.oe
.eq(gpio_oe_test
[0])
193 m
.d
.comb
+= gpio
.gpio1
.oe
.eq(gpio_oe_test
[1])
194 m
.d
.comb
+= gpio
.gpio2
.oe
.eq(gpio_oe_test
[2])
195 m
.d
.comb
+= gpio
.gpio3
.oe
.eq(gpio_oe_test
[3])
197 # get the UART resource, mess with the output tx
198 uart
= self
.jtag
.request('uart')
199 print ("uart fields", uart
, uart
.fields
)
200 self
.intermediary
= Signal()
201 m
.d
.comb
+= uart
.tx
.eq(self
.intermediary
)
202 m
.d
.comb
+= self
.intermediary
.eq(uart
.rx
)
206 i2c_sda_oe_test
= Signal(num_i2c
)
207 i2c_scl_oe_test
= Signal(num_i2c
)
208 i2c
= self
.jtag
.request('i2c')
209 print ("i2c fields", i2c
, i2c
.fields
)
210 # Connect in loopback
211 m
.d
.comb
+= i2c
.scl
.o
.eq(i2c
.scl
.i
)
212 m
.d
.comb
+= i2c
.sda
.o
.eq(i2c
.sda
.i
)
213 # Connect output enable to test port for sim
214 m
.d
.comb
+= i2c
.sda
.oe
.eq(i2c_sda_oe_test
)
215 m
.d
.comb
+= i2c
.scl
.oe
.eq(i2c_scl_oe_test
)
217 # to even be able to get at objects, you first have to make them
218 # available - i.e. not as local variables
219 # Public attributes are equivalent to input/output ports in hdl's
223 self
.i2c_sda_oe_test
= i2c_sda_oe_test
224 self
.i2c_scl_oe_test
= i2c_scl_oe_test
225 self
.gpio_i_ro
= gpio_i_ro
226 self
.gpio_o_test
= gpio_o_test
227 self
.gpio_oe_test
= gpio_oe_test
229 # sigh these wire up to the pads so you cannot set Signals
230 # that are already wired
231 if self
.no_jtag_connect
: # bypass jtag pad connect for testing purposes
233 return self
.jtag
.boundary_elaborate(m
, platform
)
239 yield from self
.jtag
.iter_ports()
242 _trellis_command_templates = [
244 {{invoke_tool("yosys")}}
246 {{get_override("yosys_opts")|options}}
253 # sigh, have to create a dummy platform for now.
254 # TODO: investigate how the heck to get it to output ilang. or verilog.
255 # or, anything, really. but at least it doesn't barf
256 class ASICPlatform(TemplatedPlatform
):
258 resources
= OrderedDict()
260 command_templates
= ['/bin/true'] # no command needed: stops barfing
262 **TemplatedPlatform
.build_script_templates
,
267 "{{name}}.debug.v": r
"""
268 /* {{autogenerated}} */
269 {{emit_debug_verilog()}}
273 default_clk
= "clk" # should be picked up / overridden by platform sys.clk
274 default_rst
= "rst" # should be picked up / overridden by platform sys.rst
276 def __init__(self
, resources
, jtag
):
280 # create set of pin resources based on the pinset, this is for the core
281 #jtag_resources = self.jtag.pad_mgr.resources
282 self
.add_resources(resources
)
284 # add JTAG without scan
285 self
.add_resources([JTAGResource('jtag', 0)], no_boundary_scan
=True)
287 def add_resources(self
, resources
, no_boundary_scan
=False):
288 print ("ASICPlatform add_resources", resources
)
289 return super().add_resources(resources
)
291 #def iter_ports(self):
292 # yield from super().iter_ports()
293 # for io in self.jtag.ios.values():
294 # print ("iter ports", io.layout, io)
295 # for field in io.core.fields:
296 # yield getattr(io.core, field)
297 # for field in io.pad.fields:
298 # yield getattr(io.pad, field)
300 # XXX these aren't strictly necessary right now but the next
301 # phase is to add JTAG Boundary Scan so it maaay be worth adding?
302 # at least for the print statements
303 def get_input(self
, pin
, port
, attrs
, invert
):
304 self
._check
_feature
("single-ended input", pin
, attrs
,
305 valid_xdrs
=(0,), valid_attrs
=None)
308 print (" get_input", pin
, "port", port
, port
.layout
)
309 m
.d
.comb
+= pin
.i
.eq(self
._invert
_if
(invert
, port
))
312 def get_output(self
, pin
, port
, attrs
, invert
):
313 self
._check
_feature
("single-ended output", pin
, attrs
,
314 valid_xdrs
=(0,), valid_attrs
=None)
317 print (" get_output", pin
, "port", port
, port
.layout
)
318 m
.d
.comb
+= port
.eq(self
._invert
_if
(invert
, pin
.o
))
321 def get_tristate(self
, pin
, port
, attrs
, invert
):
322 self
._check
_feature
("single-ended tristate", pin
, attrs
,
323 valid_xdrs
=(0,), valid_attrs
=None)
325 print (" get_tristate", pin
, "port", port
, port
.layout
)
327 print (" pad", pin
, port
, attrs
)
328 print (" pin", pin
.layout
)
330 # m.submodules += Instance("$tribuf",
333 # i_A=self._invert_if(invert, pin.o),
336 m
.d
.comb
+= io
.core
.o
.eq(pin
.o
)
337 m
.d
.comb
+= io
.core
.oe
.eq(pin
.oe
)
338 m
.d
.comb
+= pin
.i
.eq(io
.core
.i
)
339 m
.d
.comb
+= io
.pad
.i
.eq(port
.i
)
340 m
.d
.comb
+= port
.o
.eq(io
.pad
.o
)
341 m
.d
.comb
+= port
.oe
.eq(io
.pad
.oe
)
344 def get_input_output(self
, pin
, port
, attrs
, invert
):
345 self
._check
_feature
("single-ended input/output", pin
, attrs
,
346 valid_xdrs
=(0,), valid_attrs
=None)
348 print (" get_input_output", pin
, "port", port
, port
.layout
)
350 print (" port layout", port
.layout
)
352 print (" layout", pin
.layout
)
353 #m.submodules += Instance("$tribuf",
356 # i_A=self._invert_if(invert, io.pad.o),
359 # Create aliases for the port sub-signals
364 m
.d
.comb
+= pin
.i
.eq(self
._invert
_if
(invert
, port_i
))
365 m
.d
.comb
+= port_o
.eq(self
._invert
_if
(invert
, pin
.o
))
366 m
.d
.comb
+= port_oe
.eq(pin
.oe
)
370 def toolchain_prepare(self
, fragment
, name
, **kwargs
):
371 """override toolchain_prepare in order to grab the fragment
373 self
.fragment
= fragment
374 return super().toolchain_prepare(fragment
, name
, **kwargs
)
379 print("Starting sanity test case!")
380 print("printing out list of stuff in top")
381 print ("JTAG IOs", top
.jtag
.ios
)
382 # ok top now has a variable named "gpio", let's enumerate that too
383 print("printing out list of stuff in top.gpio and its type")
384 print(top
.gpio
.__class
__.__name
__, dir(top
.gpio
))
385 # ok, it's a nmigen Record, therefore it has a layout. let's print
387 print("top.gpio is a Record therefore has fields and a layout")
388 print(" layout:", top
.gpio
.layout
)
389 print(" fields:", top
.gpio
.fields
)
390 print("Fun never ends...")
391 print(" layout, gpio2:", top
.gpio
.layout
['gpio2'])
392 print(" fields, gpio2:", top
.gpio
.fields
['gpio2'])
393 print(top
.jtag
.__class
__.__name
__, dir(top
.jtag
))
395 print(top
.jtag
.resource_table_pads
[('gpio', 0)])
397 # etc etc. you get the general idea
399 yield top
.uart
.rx
.eq(0)
400 yield Delay(delayVal
)
402 yield top
.gpio
.gpio2
.o
.eq(0)
403 yield top
.gpio
.gpio3
.o
.eq(1)
405 yield top
.gpio
.gpio3
.oe
.eq(1)
407 yield top
.gpio
.gpio3
.oe
.eq(0)
408 # grab the JTAG resource pad
409 gpios_pad
= top
.jtag
.resource_table_pads
[('gpio', 0)]
410 yield gpios_pad
.gpio3
.i
.eq(1)
411 yield Delay(delayVal
)
413 yield top
.gpio
.gpio2
.oe
.eq(1)
414 yield top
.gpio
.gpio3
.oe
.eq(1)
415 yield gpios_pad
.gpio3
.i
.eq(0)
416 yield top
.jtag
.gpio
.gpio2
.i
.eq(1)
417 yield Delay(delayVal
)
421 # get a value first (as an integer). you were trying to set
422 # it to the actual Signal. this is not going to work. or if
423 # it does, it's very scary.
424 gpio_o2
= not gpio_o2
425 yield top
.gpio
.gpio2
.o
.eq(gpio_o2
)
427 # ditto: here you are trying to set to an AST expression
428 # which is inadviseable (likely to fail)
429 gpio_o3
= not gpio_o2
430 yield top
.gpio
.gpio3
.o
.eq(gpio_o3
)
431 yield Delay(delayVal
)
433 # grab the JTAG resource pad
434 uart_pad
= top
.jtag
.resource_table_pads
[('uart', 0)]
435 yield uart_pad
.rx
.i
.eq(gpio_o2
)
436 yield Delay(delayVal
)
438 yield # one clock cycle
439 tx_val
= yield uart_pad
.tx
.o
440 print ("xmit uart", tx_val
, gpio_o2
)
442 print ("jtag pad table keys")
443 print (top
.jtag
.resource_table_pads
.keys())
444 uart_pad
= top
.jtag
.resource_table_pads
[('uart', 0)]
445 print ("uart pad", uart_pad
)
446 print ("uart pad", uart_pad
.layout
)
448 yield top
.gpio
.gpio2
.oe
.eq(0)
449 yield top
.gpio
.gpio3
.oe
.eq(0)
450 yield top
.jtag
.gpio
.gpio2
.i
.eq(0)
451 yield Delay(delayVal
)
454 # Code borrowed from cesar, runs, but shouldn't actually work because of
455 # self. statements and non-existent signal names.
457 print("Example test case")
460 # Settle() is needed to give a quick response to
461 # the zero delay case
463 # wait for rel_o to become active
464 while not (yield self
.rel_o
):
467 # read the transaction parameters
468 assert self
.expecting
, "an unexpected result was produced"
469 delay
= (yield self
.delay
)
470 expected
= (yield self
.expected
)
471 # wait for `delay` cycles
472 for _
in range(delay
):
474 # activate go_i for one cycle
475 yield self
.go_i
.eq(1)
476 yield self
.count
.eq(self
.count
+ 1)
478 # check received data against the expected value
479 result
= (yield self
.port
)
480 assert result
== expected
,\
481 f
"expected {expected}, received {result}"
482 yield self
.go_i
.eq(0)
483 yield self
.port
.eq(0)
486 print("Starting GPIO test case!")
488 num_gpios
= top
.gpio_o_test
.width
489 # Grab GPIO outpud pad resource from JTAG BS - end of chain
490 print (top
.jtag
.boundary_scan_pads
.keys())
491 gpio0_o
= top
.jtag
.boundary_scan_pads
['gpio_0__gpio0__o']['o']
492 gpio1_o
= top
.jtag
.boundary_scan_pads
['gpio_0__gpio1__o']['o']
493 gpio2_o
= top
.jtag
.boundary_scan_pads
['gpio_0__gpio2__o']['o']
494 gpio3_o
= top
.jtag
.boundary_scan_pads
['gpio_0__gpio3__o']['o']
495 gpio_pad_out
= [ gpio0_o
, gpio1_o
, gpio2_o
, gpio3_o
]
497 # Grab GPIO output enable pad resource from JTAG BS - end of chain
498 gpio0_oe
= top
.jtag
.boundary_scan_pads
['gpio_0__gpio0__oe']['o']
499 gpio1_oe
= top
.jtag
.boundary_scan_pads
['gpio_0__gpio1__oe']['o']
500 gpio2_oe
= top
.jtag
.boundary_scan_pads
['gpio_0__gpio2__oe']['o']
501 gpio3_oe
= top
.jtag
.boundary_scan_pads
['gpio_0__gpio3__oe']['o']
502 gpio_pad_oe
= [gpio0_oe
, gpio1_oe
, gpio2_oe
, gpio3_oe
]
504 # Grab GPIO input pad resource from JTAG BS - start of chain
505 gpio0_pad_in
= top
.jtag
.boundary_scan_pads
['gpio_0__gpio0__i']['i']
506 gpio1_pad_in
= top
.jtag
.boundary_scan_pads
['gpio_0__gpio1__i']['i']
507 gpio2_pad_in
= top
.jtag
.boundary_scan_pads
['gpio_0__gpio2__i']['i']
508 gpio3_pad_in
= top
.jtag
.boundary_scan_pads
['gpio_0__gpio3__i']['i']
509 gpio_pad_in
= [gpio0_pad_in
, gpio1_pad_in
, gpio2_pad_in
, gpio3_pad_in
]
511 # Have the sim run through a for-loop where the gpio_o_test is
512 # incremented like a counter (0000, 0001...)
513 # At each iteration of the for-loop, assert:
514 # + output set at core matches output seen at pad
515 # TODO + input set at pad matches input seen at core
516 # TODO + if gpio_o_test bit is cleared, output seen at pad matches
518 num_gpio_o_states
= num_gpios
**2
519 pad_out
= [0] * num_gpios
520 pad_oe
= [0] * num_gpios
521 #print("Num of permutations of gpio_o_test record: ", num_gpio_o_states)
522 for gpio_o_val
in range(0, num_gpio_o_states
):
523 yield top
.gpio_o_test
.eq(gpio_o_val
)
525 yield # Move to the next clk cycle
527 # Cycle through all input combinations
528 for gpio_i_val
in range(0, num_gpio_o_states
):
529 # Set each gpio input at pad to test value
530 for gpio_bit
in range(0, num_gpios
):
531 yield gpio_pad_in
[gpio_bit
].eq((gpio_i_val
>> gpio_bit
) & 0x1)
533 # After changing the gpio0/1/2/3 inputs,
534 # the output is also going to change.
535 # *therefore it must be read again* to get the
536 # snapshot (as a python value)
537 for gpio_bit
in range(0, num_gpios
):
538 pad_out
[gpio_bit
] = yield gpio_pad_out
[gpio_bit
]
540 for gpio_bit
in range(0, num_gpios
):
541 # check core and pad in
542 gpio_i_ro
= yield top
.gpio_i_ro
[gpio_bit
]
543 out_test_bit
= ((gpio_o_val
& (1 << gpio_bit
)) != 0)
544 in_bit
= ((gpio_i_val
& (1 << gpio_bit
)) != 0)
545 # Check that the core end input matches pad
546 assert in_bit
== gpio_i_ro
547 # Test that the output at pad matches:
548 # Pad output == given test output XOR test input
549 assert (out_test_bit ^ in_bit
) == pad_out
[gpio_bit
]
551 # For debugging - VERY verbose
552 #print("---------------------")
553 #print("Test Out: ", bin(gpio_o_val))
554 #print("Test Input: ", bin(gpio_i_val))
556 #print("Pad Output: ", list(reversed(pad_out)))
557 #print("---------------------")
559 # For-loop for testing output enable signals
560 for gpio_o_val
in range(0, num_gpio_o_states
):
561 yield top
.gpio_oe_test
.eq(gpio_o_val
)
562 yield # Move to the next clk cycle
564 for gpio_bit
in range(0, num_gpios
):
565 pad_oe
[gpio_bit
] = yield gpio_pad_oe
[gpio_bit
]
568 for gpio_bit
in range(0, num_gpios
):
569 oe_test_bit
= ((gpio_o_val
& (1 << gpio_bit
)) != 0)
570 # oe set at core matches oe seen at pad:
571 assert oe_test_bit
== pad_oe
[gpio_bit
]
572 # For debugging - VERY verbose
573 #print("---------------------")
574 #print("Test Output Enable: ", bin(gpio_o_val))
576 #print("Pad Output Enable: ", list(reversed(pad_oe)))
577 #print("---------------------")
578 print("GPIO Test PASSED!")
581 # grab the JTAG resource pad
582 uart_pad
= top
.jtag
.resource_table_pads
[('uart', 0)]
584 print ("uart pad", uart_pad
)
585 print ("uart pad", uart_pad
.layout
)
587 # Test UART by writing 0 and 1 to RX
588 # Internally TX connected to RX,
589 # so match pad TX with RX
590 for i
in range(0, 2):
591 yield uart_pad
.rx
.i
.eq(i
)
593 yield # one clock cycle
594 tx_val
= yield uart_pad
.tx
.o
595 print ("xmit uart", tx_val
, 1)
598 print("UART Test PASSED!")
601 i2c_sda_i_pad
= top
.jtag
.boundary_scan_pads
['i2c_0__sda__i']['i']
602 i2c_sda_o_pad
= top
.jtag
.boundary_scan_pads
['i2c_0__sda__o']['o']
603 i2c_sda_oe_pad
= top
.jtag
.boundary_scan_pads
['i2c_0__sda__oe']['o']
605 i2c_scl_i_pad
= top
.jtag
.boundary_scan_pads
['i2c_0__scl__i']['i']
606 i2c_scl_o_pad
= top
.jtag
.boundary_scan_pads
['i2c_0__scl__o']['o']
607 i2c_scl_oe_pad
= top
.jtag
.boundary_scan_pads
['i2c_0__scl__oe']['o']
609 #i2c_pad = top.jtag.resource_table_pads[('i2c', 0)]
610 #print ("i2c pad", i2c_pad)
611 #print ("i2c pad", i2c_pad.layout)
613 for i
in range(0, 2):
614 yield i2c_sda_i_pad
.eq(i
) #i2c_pad.sda.i.eq(i)
615 yield i2c_scl_i_pad
.eq(i
) #i2c_pad.scl.i.eq(i)
616 yield top
.i2c_sda_oe_test
.eq(i
)
617 yield top
.i2c_scl_oe_test
.eq(i
)
619 yield # one clock cycle
620 sda_o_val
= yield i2c_sda_o_pad
621 scl_o_val
= yield i2c_scl_o_pad
622 sda_oe_val
= yield i2c_sda_oe_pad
623 scl_oe_val
= yield i2c_scl_oe_pad
624 print ("Test input: ", i
, " SDA/SCL out: ", sda_o_val
, scl_o_val
,
625 " SDA/SCL oe: ", sda_oe_val
, scl_oe_val
)
626 assert sda_o_val
== i
627 assert scl_o_val
== i
628 assert sda_oe_val
== i
629 assert scl_oe_val
== i
631 print("I2C Test PASSED!")
635 def test_debug_print():
636 print("Test used for getting object methods/information")
637 print("Moved here to clear clutter of gpio test")
639 print ("printing out info about the resource gpio0")
640 print (top
.gpio
['gpio0']['i'])
641 print ("this is a PIN resource", type(top
.gpio
['gpio0']['i']))
642 # yield can only be done on SIGNALS or RECORDS,
643 # NOT Pins/Resources gpio0_core_in = yield top.gpio['gpio0']['i']
644 #print("Test gpio0 core in: ", gpio0_core_in)
647 print(top
.jtag
.__class
__.__name
__, dir(top
.jtag
))
649 print(top
.__class
__.__name
__, dir(top
))
651 print(top
.ports
.__class
__.__name
__, dir(top
.ports
))
653 print(top
.gpio
.__class
__.__name
__, dir(top
.gpio
))
656 print(dir(top
.jtag
.boundary_scan_pads
['uart_0__rx__pad__i']))
657 print(top
.jtag
.boundary_scan_pads
['uart_0__rx__pad__i'].keys())
658 print(top
.jtag
.boundary_scan_pads
['uart_0__tx__pad__o'])
659 #print(type(top.jtag.boundary_scan_pads['uart_0__rx__pad__i']['rx']))
660 print ("jtag pad table keys")
661 print (top
.jtag
.resource_table_pads
.keys())
664 print(top
.jtag
.resource_table_pads
)
665 print(top
.jtag
.boundary_scan_pads
)
668 # Trying to read input from core side, looks like might be a pin...
669 # XXX don't "look like" - don't guess - *print it out*
670 #print ("don't guess, CHECK", type(top.gpio.gpio0.i))
672 print () # extra print to divide the output
675 if __name__
== '__main__':
677 and to create a Platform instance with that list, and build
681 p.resources=listofstuff
684 pinset
= dummy_pinset()
686 resources
= create_resources(pinset
)
687 top
= Blinker(pinset
, resources
, no_jtag_connect
=False)#True)
689 vl
= rtlil
.convert(top
, ports
=top
.ports())
690 with
open("test_jtag_blinker.il", "w") as f
:
694 # XXX these modules are all being added *AFTER* the build process links
695 # everything together. the expectation that this would work is...
696 # unrealistic. ordering, clearly, is important.
698 # dut = JTAG(test_pinset(), wb_data_wid=64, domain="sync")
699 top
.jtag
.stop
= False
700 # rather than the client access the JTAG bus directly
701 # create an alternative that the client sets
704 cdut
.cbus
= JTAGInterface()
706 # set up client-server on port 44843-something
707 top
.jtag
.s
= JTAGServer()
708 cdut
.c
= JTAGClient()
709 top
.jtag
.s
.get_connection()
711 # print ("running server only as requested,
712 # use openocd remote to test")
714 # top.jtag.s.get_connection(None) # block waiting for connection
716 # take copy of ir_width and scan_len
717 cdut
._ir
_width
= top
.jtag
._ir
_width
718 cdut
.scan_len
= top
.jtag
.scan_len
720 p
= ASICPlatform (resources
, top
.jtag
)
722 # this is what needs to gets treated as "top", after "main module" top
723 # is augmented with IO pads with JTAG tacked on. the expectation that
724 # the get_input() etc functions will be called magically by some other
725 # function is unrealistic.
726 top_fragment
= p
.fragment
728 # XXX simulating top (the module that does not itself contain IO pads
729 # because that's covered by build) cannot possibly be expected to work
730 # particularly when modules have been added *after* the platform build()
731 # function has been called.
734 sim
.add_clock(1e-6, domain
="sync") # standard clock
736 #sim.add_sync_process(wrap(jtag_srv(top))) #? jtag server
737 #if len(sys.argv) != 2 or sys.argv[1] != 'server':
739 #sim.add_sync_process(wrap(jtag_sim(cdut, top.jtag)))
740 # handles (pretends to be) DMI
741 #sim.add_sync_process(wrap(dmi_sim(top.jtag)))
743 #sim.add_sync_process(wrap(test_case1()))
744 #sim.add_sync_process(wrap(test_case0()))
746 #sim.add_sync_process(wrap(test_gpios()))
747 sim
.add_sync_process(wrap(test_uart()))
748 sim
.add_sync_process(wrap(test_i2c()))
749 #sim.add_sync_process(wrap(test_debug_print()))
751 with sim
.write_vcd("blinker_test.vcd"):