7654d177756ae48db4ccf1735f27d735b8341d2d
2 from nmigen
.build
.dsl
import Resource
, Subsignal
, Pins
3 from nmigen
.build
.plat
import TemplatedPlatform
4 from nmigen
.build
.res
import ResourceManager
, ResourceError
5 from nmigen
import Elaboratable
, Signal
, Module
, Instance
6 from collections
import OrderedDict
7 from jtag
import JTAG
, resiotypes
8 from copy
import deepcopy
10 # Was thinking of using these functions, but skipped for simplicity for now
11 # XXX nope. the output from JSON file.
12 #from pinfunctions import (i2s, lpc, emmc, sdmmc, mspi, mquadspi, spi,
13 # quadspi, i2c, mi2c, jtag, uart, uartfull, rgbttl, ulpi, rgmii, flexbus1,
14 # flexbus2, sdram1, sdram2, sdram3, vss, vdd, sys, eint, pwm, gpio)
16 # File for stage 1 pinmux tested proposed by Luke,
17 # https://bugs.libre-soc.org/show_bug.cgi?id=50#c10
21 # sigh this needs to come from pinmux.
24 gpios
.append("%d*" % i
)
25 return {'uart': ['tx+', 'rx-'],
27 'i2c': ['sda*', 'scl+']}
30 a function is needed which turns the results of dummy_pinset()
33 [UARTResource("uart", 0, tx=..., rx=..),
34 I2CResource("i2c", 0, scl=..., sda=...),
35 Resource("gpio", 0, Subsignal("i"...), Subsignal("o"...)
36 Resource("gpio", 1, Subsignal("i"...), Subsignal("o"...)
42 def create_resources(pinset
):
44 for periph
, pins
in pinset
.items():
47 #print("I2C required!")
48 resources
.append(I2CResource('i2c', 0, sda
='sda', scl
='scl'))
49 elif periph
== 'uart':
50 #print("UART required!")
51 resources
.append(UARTResource('uart', 0, tx
='tx', rx
='rx'))
52 elif periph
== 'gpio':
53 #print("GPIO required!")
54 print ("GPIO is defined as '*' type, meaning i, o and oe needed")
57 pname
= "gpio"+pin
[:-1] # strip "*" on end
59 # urrrr... tristsate and io assume a single pin which is
60 # of course exactly what we don't want in an ASIC: we want
61 # *all three* pins but the damn port is not outputted
62 # as a triplet, it's a single Record named "io". sigh.
63 # therefore the only way to get a triplet of i/o/oe
64 # is to *actually* create explicit triple pins
65 pads
.append(Subsignal("i",
66 Pins(pname
+"_i", dir="i", assert_width
=1)))
67 pads
.append(Subsignal("o",
68 Pins(pname
+"_o", dir="o", assert_width
=1)))
69 pads
.append(Subsignal("oe",
70 Pins(pname
+"_oe", dir="oe", assert_width
=1)))
71 ios
.append(Resource
.family(pname
, 0, default_name
=pname
,
73 resources
.append(Resource
.family(periph
, 0, default_name
="gpio",
77 clk
= Resource("clk", 0, Pins("sys_clk", dir="i"))
78 rst
= Resource("rst", 0, Pins("sys_rst", dir="i"))
84 def UARTResource(*args
, rx
, tx
):
86 io
.append(Subsignal("rx", Pins(rx
, dir="i", assert_width
=1)))
87 io
.append(Subsignal("tx", Pins(tx
, dir="o", assert_width
=1)))
88 return Resource
.family(*args
, default_name
="uart", ios
=io
)
91 def I2CResource(*args
, scl
, sda
):
93 io
.append(Subsignal("scl", Pins(scl
, dir="io", assert_width
=1)))
94 io
.append(Subsignal("sda", Pins(sda
, dir="io", assert_width
=1)))
95 return Resource
.family(*args
, default_name
="i2c", ios
=io
)
98 # ridiculously-simple top-level module. doesn't even have a sync domain
99 # and can't have one until a clock has been established by ASICPlatform.
100 class Blinker(Elaboratable
):
101 def __init__(self
, pinset
):
102 self
.jtag
= JTAG({}, "sync")
104 def elaborate(self
, platform
):
106 m
.submodules
.jtag
= self
.jtag
108 m
.d
.sync
+= count
.eq(5)
109 print ("resources", platform
.resources
.items())
110 gpio
= platform
.request('gpio')
111 print (gpio
, gpio
.layout
, gpio
.fields
)
112 # get the GPIO bank, mess about with some of the pins
113 m
.d
.comb
+= gpio
.gpio0
.o
.eq(1)
114 m
.d
.comb
+= gpio
.gpio1
.o
.eq(gpio
.gpio2
.i
)
115 m
.d
.comb
+= gpio
.gpio1
.oe
.eq(count
[4])
116 m
.d
.sync
+= count
[0].eq(gpio
.gpio1
.i
)
117 # get the UART resource, mess with the output tx
118 uart
= platform
.request('uart')
119 print (uart
, uart
.fields
)
120 m
.d
.comb
+= uart
.tx
.eq(1)
125 _trellis_command_templates = [
127 {{invoke_tool("yosys")}}
129 {{get_override("yosys_opts")|options}}
136 # sigh, have to create a dummy platform for now.
137 # TODO: investigate how the heck to get it to output ilang. or verilog.
138 # or, anything, really. but at least it doesn't barf
139 class ASICPlatform(TemplatedPlatform
):
141 resources
= OrderedDict()
143 command_templates
= ['/bin/true']
145 **TemplatedPlatform
.build_script_templates
,
150 "{{name}}.debug.v": r
"""
151 /* {{autogenerated}} */
152 {{emit_debug_verilog()}}
156 default_clk
= "clk" # should be picked up / overridden by platform sys.clk
157 default_rst
= "rst" # should be picked up / overridden by platform sys.rst
159 def __init__(self
, resources
, jtag
):
160 self
.pad_mgr
= ResourceManager([], [])
163 # create set of pin resources based on the pinset, this is for the core
164 self
.add_resources(resources
)
165 # record resource lookup between core IO names and pads
168 def request(self
, name
, number
=0, *, dir=None, xdr
=None):
169 """request a Resource (e.g. name="uart", number=0) which will
170 return a data structure containing Records of all the pins.
172 this override will also - automatically - create a JTAG Boundary Scan
173 connection *without* any change to the actual Platform.request() API
175 # okaaaay, bit of shenanigens going on: the important data structure
176 # here is Resourcemanager._ports. requests add to _ports, which is
177 # what needs redirecting. therefore what has to happen is to
178 # capture the number of ports *before* the request. sigh.
179 start_ports
= len(self
._ports
)
180 value
= super().request(name
, number
, dir=dir, xdr
=xdr
)
181 end_ports
= len(self
._ports
)
183 # now make a corresponding (duplicate) request to the pad manager
184 # BUT, if it doesn't exist, don't sweat it: all it means is, the
185 # application did not request Boundary Scan for that resource.
186 pad_start_ports
= len(self
.pad_mgr
._ports
)
188 pvalue
= self
.pad_mgr
.request(name
, number
, dir=dir, xdr
=xdr
)
189 except AssertionError:
191 pad_end_ports
= len(self
.pad_mgr
._ports
)
193 # ok now we have the lengths: now create a lookup between the pad
194 # and the core, so that JTAG boundary scan can be inserted in between
195 core
= self
._ports
[start_ports
:end_ports
]
196 pads
= self
.pad_mgr
._ports
[pad_start_ports
:pad_end_ports
]
197 # oops if not the same numbers added. it's a duplicate. shouldn't happen
198 assert len(core
) == len(pads
), "argh, resource manager error"
202 # pad/core each return a list of tuples of (res, pin, port, attrs)
203 for pad
, core
in zip(pads
, core
):
204 # create a lookup on pin name to get at the hidden pad instance
205 # this pin name will be handed to get_input, get_output etc.
206 # and without the padlookup you can't find the (duplicate) pad.
207 # note that self.padlookup and self.jtag.ios use the *exact* same
211 if pin
is None: continue # skip when pin is None
212 assert corepin
is not None # if pad was None, core should be too
213 print ("iter", pad
, pin
.name
)
214 assert pin
.name
not in self
.padlookup
# no overwrites allowed!
215 assert pin
.name
== corepin
.name
# has to be the same!
216 self
.padlookup
[pin
.name
] = pad
# store pad by pin name
218 # now add the IO Shift Register. first identify the type
219 # then request a JTAG IOConn. we can't wire it up (yet) because
220 # we don't have a Module() instance. doh. that comes in get_input
221 # and get_output etc. etc.
222 iotype
= resiotypes
[pin
.dir] # look up the C4M-JTAG IOType
223 io
= self
.jtag
.add_io(iotype
=iotype
, name
=pin
.name
) # create IOConn
224 self
.jtag
.ios
[pin
.name
] = io
# store IOConn Record by pin name
226 # finally return the value just like ResourceManager.request()
229 def add_resources(self
, resources
, no_boundary_scan
=False):
230 super().add_resources(resources
)
233 # make a *second* - identical - set of pin resources for the IO ring
234 padres
= deepcopy(resources
)
235 self
.pad_mgr
.add_resources(padres
)
237 # XXX these aren't strictly necessary right now but the next
238 # phase is to add JTAG Boundary Scan so it maaay be worth adding?
239 # at least for the print statements
240 def get_input(self
, pin
, port
, attrs
, invert
):
241 self
._check
_feature
("single-ended input", pin
, attrs
,
242 valid_xdrs
=(0,), valid_attrs
=None)
245 print (" get_input", pin
, "port", port
, port
.layout
)
246 if pin
.name
in ['clk_0', 'rst_0']: # sigh
247 # simple pass-through from port to pin
248 print("No JTAG chain in-between")
249 m
.d
.comb
+= pin
.i
.eq(self
._invert
_if
(invert
, port
))
251 (res
, pin
, port
, attrs
) = self
.padlookup
[pin
.name
]
252 io
= self
.jtag
.ios
[pin
.name
]
253 print (" pad", res
, pin
, port
, attrs
)
254 print (" pin", pin
.layout
)
255 print (" jtag", io
.core
.layout
, io
.pad
.layout
)
256 m
.d
.comb
+= io
.pad
.i
.eq(self
._invert
_if
(invert
, port
))
257 m
.d
.comb
+= pin
.i
.eq(io
.core
.i
)
260 def get_output(self
, pin
, port
, attrs
, invert
):
261 self
._check
_feature
("single-ended output", pin
, attrs
,
262 valid_xdrs
=(0,), valid_attrs
=None)
265 print (" get_output", pin
, "port", port
, port
.layout
)
266 if pin
.name
in ['clk_0', 'rst_0']: # sigh
267 # simple pass-through from pin to port
268 print("No JTAG chain in-between")
269 m
.d
.comb
+= port
.eq(self
._invert
_if
(invert
, pin
.o
))
271 (res
, pin
, port
, attrs
) = self
.padlookup
[pin
.name
]
272 io
= self
.jtag
.ios
[pin
.name
]
273 print (" pad", res
, pin
, port
, attrs
)
274 print (" pin", pin
.layout
)
275 print (" jtag", io
.core
.layout
, io
.pad
.layout
)
276 m
.d
.comb
+= port
.eq(self
._invert
_if
(invert
, io
.pad
.o
))
277 m
.d
.comb
+= pin
.o
.eq(io
.core
.o
)
280 def get_tristate(self
, pin
, port
, attrs
, invert
):
281 self
._check
_feature
("single-ended tristate", pin
, attrs
,
282 valid_xdrs
=(0,), valid_attrs
=None)
284 print (" get_tristate", pin
, "port", port
, port
.layout
)
286 if pin
.name
in ['clk_0', 'rst_0']: # sigh
287 print("No JTAG chain in-between")
288 # Can port's i/o/oe be accessed like this?
289 m
.d
.comb
+= port
.o
.eq(pin
.o
)
290 m
.d
.comb
+= port
.oe
.eq(pin
.oe
)
291 m
.d
.comb
+= pin
.i
.eq(port
.i
)
293 (res
, pin
, port
, attrs
) = self
.padlookup
[pin
.name
]
294 io
= self
.jtag
.ios
[pin
.name
]
295 print (" pad", res
, pin
, port
, attrs
)
296 print (" pin", pin
.layout
)
297 print (" jtag", io
.core
.layout
, io
.pad
.layout
)
298 m
.d
.comb
+= io
.core
.o
.eq(pin
.o
)
299 m
.d
.comb
+= io
.core
.oe
.eq(pin
.oe
)
300 m
.d
.comb
+= pin
.i
.eq(io
.core
.i
)
301 m
.d
.comb
+= io
.pad
.i
.eq(port
.i
)
302 m
.d
.comb
+= port
.o
.eq(io
.pad
.o
)
303 m
.d
.comb
+= port
.oe
.eq(io
.pad
.oe
)
306 def get_input_output(self
, pin
, port
, attrs
, invert
):
307 self
._check
_feature
("single-ended input/output", pin
, attrs
,
308 valid_xdrs
=(0,), valid_attrs
=None)
310 print (" get_input_output", pin
, "port", port
, port
.layout
)
312 if pin
.name
in ['clk_0', 'rst_0']: # sigh
313 print("No JTAG chain in-between")
314 m
.submodules
+= Instance("$tribuf",
317 i_A
=self
._invert
_if
(invert
, pin
.o
),
320 m
.d
.comb
+= pin
.i
.eq(self
._invert
_if
(invert
, port
))
322 (res
, pin
, port
, attrs
) = self
.padlookup
[pin
.name
]
323 io
= self
.jtag
.ios
[pin
.name
]
324 print (" pad", res
, pin
, port
, attrs
)
325 print (" pin", pin
.layout
)
326 print (" jtag", io
.core
.layout
, io
.pad
.layout
)
327 m
.submodules
+= Instance("$tribuf",
330 i_A
=self
._invert
_if
(invert
, io
.pad
.o
),
333 m
.d
.comb
+= io
.pad
.i
.eq(self
._invert
_if
(invert
, port
))
334 m
.d
.comb
+= pin
.i
.eq(io
.core
.i
)
335 m
.d
.comb
+= io
.core
.o
.eq(pin
.o
)
336 m
.d
.comb
+= io
.core
.oe
.eq(pin
.oe
)
341 and to create a Platform instance with that list, and build
345 p.resources=listofstuff
348 pinset
= dummy_pinset()
349 top
= Blinker(pinset
)
351 resources
= create_resources(pinset
)
352 p
= ASICPlatform (resources
, top
.jtag
)