3 This BSV file has been generated by the PinMux tool available at:
4 https://bitbucket.org/casl/pinmux.
6 Authors: Neel Gala, Luke
7 Date of generation: Sun Jun 24 12:09:36 2018
12 // FunctionType: contains the active wires of a function. That INCLUDES
13 // GPIO (as GPIO is also a "Function"). These are what get muxed.
14 // However, only GPIO "Functions" will end up with Register SRAMs.
16 Bit#(1) outputval; // output from function to pad bit2
17 Bit#(1) inputval; // input from pad to function bit1
18 Bit#(1) output_en; // output enable from core to pad bit0
19 } FunctionType deriving(Eq,Bits,FShow);
22 Bit#(1) outputval; // output from core to pad bit7
23 Bit#(1) output_en; // output enable from core to pad bit6
24 Bit#(1) input_en; // input enable from core to io_cell bit5
25 } GenericIOType deriving(Eq,Bits,FShow);
27 interface MuxSelectionLines;
29 // declare the method which will capture the user pin-mux
30 // selection values.The width of the input is dependent on the number
31 // of muxes happening per IO. For now we have a generalized width
32 // where each IO will have the same number of muxes.
33 method Action cell0_mux (Bit#(1) in);
34 method Action cell1_mux (Bit#(1) in);
35 method Action cell2_mux (Bit#(1) in);
38 interface PeripheralSide;
39 // declare the interface to the IO cells.
40 // Each IO cell will have 8 input field (output from pin mux
41 // and on output field (input to pinmux)
42 // interface declaration between IO-0 and pinmux
43 (*always_ready*) method GenericIOType io0_cell;
44 (*always_ready,always_enabled,result="io"*) method
45 Action io0_inputval (Bit#(1) in);
46 // interface declaration between IO-1 and pinmux
47 (*always_ready*) method GenericIOType io1_cell;
48 (*always_ready,always_enabled,result="io"*) method
49 Action io1_inputval (Bit#(1) in);
50 // interface declaration between IO-2 and pinmux
51 (*always_ready*) method GenericIOType io2_cell;
52 (*always_ready,always_enabled,result="io"*) method
53 Action io2_inputval (Bit#(1) in);
54 // interface declaration between UART-0 and pinmux
55 (*always_ready,always_enabled*) method Action uart_tx (Bit#(1) in);
56 (*always_ready,always_enabled*) method Bit#(1) uart_rx;
57 // interface declaration between GPIOA-0 and pinmux
58 (*always_ready,always_enabled*) method Action gpioa_a0_out (Bit#(1) in);
59 (*always_ready,always_enabled*) method Action gpioa_a0_outen (Bit#(1) in);
60 (*always_ready,always_enabled*) method Bit#(1) gpioa_a0_in;
61 (*always_ready,always_enabled*) method Action gpioa_a1_out (Bit#(1) in);
62 (*always_ready,always_enabled*) method Action gpioa_a1_outen (Bit#(1) in);
63 (*always_ready,always_enabled*) method Bit#(1) gpioa_a1_in;
64 (*always_ready,always_enabled*) method Action gpioa_a2_out (Bit#(1) in);
65 (*always_ready,always_enabled*) method Action gpioa_a2_outen (Bit#(1) in);
66 (*always_ready,always_enabled*) method Bit#(1) gpioa_a2_in;
67 // interface declaration between TWI-0 and pinmux
68 (*always_ready,always_enabled*) method Action twi_sda_out (Bit#(1) in);
69 (*always_ready,always_enabled*) method Action twi_sda_outen (Bit#(1) in);
70 (*always_ready,always_enabled*) method Bit#(1) twi_sda_in;
71 (*always_ready,always_enabled*) method Action twi_scl_out (Bit#(1) in);
72 (*always_ready,always_enabled*) method Action twi_scl_outen (Bit#(1) in);
73 (*always_ready,always_enabled*) method Bit#(1) twi_scl_in;
77 interface MuxSelectionLines mux_lines;
78 interface PeripheralSide peripheral_side;
81 module mkpinmux(Ifc_pinmux);
83 // the followins wires capture the pin-mux selection
84 // values for each mux assigned to a CELL
86 Wire#(Bit#(1)) wrcell0_mux<-mkDWire(0);
87 Wire#(Bit#(1)) wrcell1_mux<-mkDWire(0);
88 Wire#(Bit#(1)) wrcell2_mux<-mkDWire(0);
89 // following wires capture signals to IO CELL if io-0 is
91 Wire#(Bit#(1)) cell0_mux_out<-mkDWire(0);
92 Wire#(Bit#(1)) cell0_mux_outen<-mkDWire(0);
93 Wire#(Bit#(1)) cell0_mux_in<-mkDWire(0);
95 // following wires capture signals to IO CELL if io-1 is
97 Wire#(Bit#(1)) cell1_mux_out<-mkDWire(0);
98 Wire#(Bit#(1)) cell1_mux_outen<-mkDWire(0);
99 Wire#(Bit#(1)) cell1_mux_in<-mkDWire(0);
101 // following wires capture signals to IO CELL if io-2 is
103 Wire#(Bit#(1)) cell2_mux_out<-mkDWire(0);
104 Wire#(Bit#(1)) cell2_mux_outen<-mkDWire(0);
105 Wire#(Bit#(1)) cell2_mux_in<-mkDWire(0);
107 // following wires capture signals to IO CELL if uart-0 is
109 Wire#(Bit#(1)) wruart_tx<-mkDWire(0);
110 Wire#(Bit#(1)) wruart_rx<-mkDWire(0);
111 # declare uart_tx_io, set up as type 'out'
112 GenericIOType uart_tx_io = GenericIOType{
117 # declare uart_rx_io, set up as type 'input'
118 GenericIOType uart_rx_io = GenericIOType{
124 // following wires capture signals to IO CELL if gpioa-0 is
126 Wire#(Bit#(1)) wrgpioa_a0_out<-mkDWire(0);
127 Wire#(Bit#(1)) wrgpioa_a0_outen<-mkDWire(0);
128 Wire#(Bit#(1)) wrgpioa_a0_in<-mkDWire(0);
129 Wire#(Bit#(1)) wrgpioa_a1_out<-mkDWire(0);
130 Wire#(Bit#(1)) wrgpioa_a1_outen<-mkDWire(0);
131 Wire#(Bit#(1)) wrgpioa_a1_in<-mkDWire(0);
132 Wire#(Bit#(1)) wrgpioa_a2_out<-mkDWire(0);
133 Wire#(Bit#(1)) wrgpioa_a2_outen<-mkDWire(0);
134 Wire#(Bit#(1)) wrgpioa_a2_in<-mkDWire(0);
135 # declare gpioa_a0_io, set up as type 'inout'
136 GenericIOType gpioa_a0_io = GenericIOType{
137 outputval:wrgpioa_a0_out,
138 output_en:wrgpioa_a0_outen,
139 input_en:~wrgpioa_a0_outen,
141 # declare gpioa_a1_io, set up as type 'inout'
142 GenericIOType gpioa_a1_io = GenericIOType{
143 outputval:wrgpioa_a1_out,
144 output_en:wrgpioa_a1_outen,
145 input_en:~wrgpioa_a1_outen,
147 # declare gpioa_a2_io, set up as type 'inout'
148 GenericIOType gpioa_a2_io = GenericIOType{
149 outputval:wrgpioa_a2_out,
150 output_en:wrgpioa_a2_outen,
151 input_en:~wrgpioa_a2_outen,
154 // following wires capture signals to IO CELL if twi-0 is
156 Wire#(Bit#(1)) wrtwi_sda_out<-mkDWire(0);
157 Wire#(Bit#(1)) wrtwi_sda_outen<-mkDWire(0);
158 Wire#(Bit#(1)) wrtwi_sda_in<-mkDWire(0);
159 Wire#(Bit#(1)) wrtwi_scl_out<-mkDWire(0);
160 Wire#(Bit#(1)) wrtwi_scl_outen<-mkDWire(0);
161 Wire#(Bit#(1)) wrtwi_scl_in<-mkDWire(0);
162 # declare twi_sda_io, set up as type 'inout'
163 GenericIOType twi_sda_io = GenericIOType{
164 outputval:wrtwi_sda_out,
165 output_en:wrtwi_sda_outen,
166 input_en:~wrtwi_sda_outen,
168 # declare twi_scl_io, set up as type 'inout'
169 GenericIOType twi_scl_io = GenericIOType{
170 outputval:wrtwi_scl_out,
171 output_en:wrtwi_scl_outen,
172 input_en:~wrtwi_scl_outen,
176 /*====== This where the muxing starts for each io-cell======*/
177 // TODO: this needs to stop using GenericIOType and
178 // set the output (and only the output) as a wire
179 // output muxer for cell idx 0
180 cell0_mux_out=wrcell0_mux==0?gpioa_a0_io:
181 wrcell0_mux==1?uart0_tx_io:
184 // TODO: here is needed something which sets a new
185 // wire, cell0_mux_outen
187 wrcell0_mux==0?gpioa_a0_io.output_en: // gpio bi-directional
188 wrcell0_mux==1?gpioa_a0_io.output_en: // i think....
189 0; // not sure.... 3rd entry is blank... might as well be 0
191 rule assign_wrgpioa_a0_in_on_cell0(wrcell0_mux==0);
192 wrgpioa_a0_in<=cell0_mux_in;
195 // TODO: this needs to stop using GenericIOType and
196 // set the output (and only the output) as a wire
197 // output muxer for cell idx 1
198 cell1_mux_out=wrcell1_mux==0?gpioa_a1_io:
199 wrcell1_mux==1?uart0_rx_io: // oink?? this is an input!!
202 // TODO: here is needed something which sets a new
203 // wire, cell1_mux_outen
205 wrcell1_mux==0?gpioa_a1_io.output_en: // gpio bi-directional
206 wrcell1_mux==1?uart0_rx_io: // oink?? this is an input!!
207 twi0_sda_io.output_en; // this one's bi-directional
209 rule assign_wrgpioa_a1_in_on_cell1(wrcell1_mux==0);
210 wrgpioa_a1_in<=cell1_mux_in;
214 rule assign_wruart0_rx_on_cell1(wrcell1_mux==1);
215 wruart0_rx<=cell1_mux_in;
219 rule assign_wrtwi0_sda_in_on_cell1(wrcell1_mux==2);
220 wrtwi0_sda_in<=cell1_mux_in;
223 // TODO: this needs to stop using GenericIOType and
224 // set the output (and only the output) as a wire
225 // output muxer for cell idx 2
227 wrcell2_mux==0?gpioa_a2_io:
231 // TODO: here is needed something which sets a new
232 // wire, cell2_mux_outen
234 wrcell2_mux==0?gpioa_a2_io.output_en:
236 twi0_scl_io.output_en;
239 rule assign_wrgpioa_a2_in_on_cell2(wrcell2_mux==0);
240 wrgpioa_a2_in<=cell2_mux_in;
244 rule assign_wrtwi0_scl_in_on_cell2(wrcell2_mux==2);
245 wrtwi0_scl_in<=cell2_mux_in;
249 /*============================================================*/
251 interface mux_lines = interface MuxSelectionLines
253 method Action cell0_mux(Bit#(1) in);
257 method Action cell1_mux(Bit#(1) in);
261 method Action cell2_mux(Bit#(1) in);
266 interface peripheral_side = interface PeripheralSide
268 method io0_cell=cell0_mux_out;
269 method Action io0_inputval(Bit#(1) in);
273 method io1_cell=cell1_mux_out;
274 method Action io1_inputval(Bit#(1) in);
278 method io2_cell=cell2_mux_out;
279 method Action io2_inputval(Bit#(1) in);
283 method Action uart_tx(Bit#(1) in);
286 method uart_rx=wruart_rx;
288 method Action gpioa_a0_out(Bit#(1) in);
291 method Action gpioa_a0_outen(Bit#(1) in);
292 wrgpioa_a0_outen<=in;
294 method gpioa_a0_in=wrgpioa_a0_in;
295 method Action gpioa_a1_out(Bit#(1) in);
298 method Action gpioa_a1_outen(Bit#(1) in);
299 wrgpioa_a1_outen<=in;
301 method gpioa_a1_in=wrgpioa_a1_in;
302 method Action gpioa_a2_out(Bit#(1) in);
305 method Action gpioa_a2_outen(Bit#(1) in);
306 wrgpioa_a2_outen<=in;
308 method gpioa_a2_in=wrgpioa_a2_in;
310 method Action twi_sda_out(Bit#(1) in);
313 method Action twi_sda_outen(Bit#(1) in);
316 method twi_sda_in=wrtwi_sda_in;
317 method Action twi_scl_out(Bit#(1) in);
320 method Action twi_scl_outen(Bit#(1) in);
323 method twi_scl_in=wrtwi_scl_in;