src/test_bsv/pinmux.bsv

   1
   2 /*
   3    This BSV file has been generated by the PinMux tool available at:
   4    https://bitbucket.org/casl/pinmux.
   5
   6    Authors: Neel Gala, Luke
   7    Date of generation: Mon Jun 25 16:20:40 2018
   8 */
   9
  10 package pinmux;
  11
  12    interface MuxSelectionLines;
  13
  14       // declare the method which will capture the user pin-mux
  15       // selection values.The width of the input is dependent on the number
  16       // of muxes happening per IO. For now we have a generalized width
  17       // where each IO will have the same number of muxes.
  18      method  Action cell0_mux (Bit#(2) in);
  19      method  Action cell1_mux (Bit#(2) in);
  20      method  Action cell2_mux (Bit#(2) in);
  21       endinterface
  22
  23
  24       interface PeripheralSide;
  25       // declare the interface to the peripherals
  26       // Each peripheral's function will be either an input, output
  27       // or be bi-directional.  an input field will be an output from the
  28       // peripheral and an output field will be an input to the peripheral.
  29       // Bi-directional functions also have an output-enable (which
  30       // again comes *in* from the peripheral)
  31           // interface declaration between IO-0 and pinmux
  32     (*always_ready,always_enabled*) method  Bit#(1) io0_cell_out;
  33     (*always_ready,always_enabled*) method  Bit#(1) io0_cell_outen;
  34     (*always_ready,always_enabled,result="io"*) method
  35                        Action io0_cell_in (Bit#(1) in);
  36           // interface declaration between IO-1 and pinmux
  37     (*always_ready,always_enabled*) method  Bit#(1) io1_cell_out;
  38     (*always_ready,always_enabled*) method  Bit#(1) io1_cell_outen;
  39     (*always_ready,always_enabled,result="io"*) method
  40                        Action io1_cell_in (Bit#(1) in);
  41           // interface declaration between IO-2 and pinmux
  42     (*always_ready,always_enabled*) method  Bit#(1) io2_cell_out;
  43     (*always_ready,always_enabled*) method  Bit#(1) io2_cell_outen;
  44     (*always_ready,always_enabled,result="io"*) method
  45                        Action io2_cell_in (Bit#(1) in);
  46       endinterface
  47
  48
  49       interface IOCellSide;
  50       // declare the interface to the IO cells.
  51       // Each IO cell will have 1 input field (output from pin mux)
  52       // and an output and out-enable field (input to pinmux)
  53           // interface declaration between UART-0 and pinmux
  54     (*always_ready,always_enabled*) method  Action uart_tx (Bit#(1) in);
  55     (*always_ready,always_enabled*) method  Bit#(1) uart_rx;
  56           // interface declaration between GPIOA-0 and pinmux
  57     (*always_ready,always_enabled*) method  Action gpioa_a0_out (Bit#(1) in);
  58     (*always_ready,always_enabled*) method  Action gpioa_a0_outen (Bit#(1) in);
  59     (*always_ready,always_enabled*) method  Bit#(1) gpioa_a0_in;
  60     (*always_ready,always_enabled*) method  Action gpioa_a1_out (Bit#(1) in);
  61     (*always_ready,always_enabled*) method  Action gpioa_a1_outen (Bit#(1) in);
  62     (*always_ready,always_enabled*) method  Bit#(1) gpioa_a1_in;
  63     (*always_ready,always_enabled*) method  Action gpioa_a2_out (Bit#(1) in);
  64     (*always_ready,always_enabled*) method  Action gpioa_a2_outen (Bit#(1) in);
  65     (*always_ready,always_enabled*) method  Bit#(1) gpioa_a2_in;
  66           // interface declaration between TWI-0 and pinmux
  67     (*always_ready,always_enabled*) method  Action twi_sda_out (Bit#(1) in);
  68     (*always_ready,always_enabled*) method  Action twi_sda_outen (Bit#(1) in);
  69     (*always_ready,always_enabled*) method  Bit#(1) twi_sda_in;
  70     (*always_ready,always_enabled*) method  Action twi_scl_out (Bit#(1) in);
  71     (*always_ready,always_enabled*) method  Action twi_scl_outen (Bit#(1) in);
  72     (*always_ready,always_enabled*) method  Bit#(1) twi_scl_in;
  73       endinterface
  74
  75
  76    interface Ifc_pinmux;
  77       // this interface controls how each IO cell is routed.  setting
  78       // any given IO cell's mux control value will result in redirection
  79       // of not just the input or output to different peripheral functions
  80       // but also the *direction* control - if appropriate - as well.
  81       interface MuxSelectionLines mux_lines;
  82
  83       // this interface contains the inputs, outputs and direction-control
  84       // lines for all peripherals.  GPIO is considered to also be just
  85       // a peripheral because it also has in, out and direction-control.
  86       interface PeripheralSide peripheral_side;
  87
  88       // this interface is to be linked to the individual IO cells.
  89       // if looking at a "non-muxed" GPIO design, basically the
  90       // IO cell input, output and direction-control wires are cut
  91       // (giving six pairs of dangling wires, named left and right)
  92       // these iocells are routed in their place on one side ("left")
  93       // and the matching *GPIO* peripheral interfaces in/out/dir
  94       // connect to the OTHER side ("right").  the result is that
  95       // the muxer settings end up controlling the routing of where
  96       // the I/O from the IOcell actually goes.
  97       interface IOCellSide iocell_side;
  98    endinterface
  99    (*synthesize*)
 100    module mkpinmux(Ifc_pinmux);
 101
 102       // the followins wires capture the pin-mux selection
 103       // values for each mux assigned to a CELL
 104
 105       Wire#(Bit#(2)) wrcell0_mux<-mkDWire(0);
 106       Wire#(Bit#(2)) wrcell1_mux<-mkDWire(0);
 107       Wire#(Bit#(2)) wrcell2_mux<-mkDWire(0);
 108       // following wires capture signals to IO CELL if io-0 is
 109       // allotted to it
 110       Wire#(Bit#(1)) cell0_mux_out<-mkDWire(0);
 111       Wire#(Bit#(1)) cell0_mux_outen<-mkDWire(0);
 112       Wire#(Bit#(1)) cell0_mux_in<-mkDWire(0);
 113
 114       // following wires capture signals to IO CELL if io-1 is
 115       // allotted to it
 116       Wire#(Bit#(1)) cell1_mux_out<-mkDWire(0);
 117       Wire#(Bit#(1)) cell1_mux_outen<-mkDWire(0);
 118       Wire#(Bit#(1)) cell1_mux_in<-mkDWire(0);
 119
 120       // following wires capture signals to IO CELL if io-2 is
 121       // allotted to it
 122       Wire#(Bit#(1)) cell2_mux_out<-mkDWire(0);
 123       Wire#(Bit#(1)) cell2_mux_outen<-mkDWire(0);
 124       Wire#(Bit#(1)) cell2_mux_in<-mkDWire(0);
 125
 126       // following wires capture signals to IO CELL if uart-0 is
 127       // allotted to it
 128       Wire#(Bit#(1)) wruart_tx<-mkDWire(0);
 129       Wire#(Bit#(1)) wruart_rx<-mkDWire(0);
 130
 131       // following wires capture signals to IO CELL if gpioa-0 is
 132       // allotted to it
 133       Wire#(Bit#(1)) wrgpioa_a0_out<-mkDWire(0);
 134       Wire#(Bit#(1)) wrgpioa_a0_outen<-mkDWire(0);
 135       Wire#(Bit#(1)) wrgpioa_a0_in<-mkDWire(0);
 136       Wire#(Bit#(1)) wrgpioa_a1_out<-mkDWire(0);
 137       Wire#(Bit#(1)) wrgpioa_a1_outen<-mkDWire(0);
 138       Wire#(Bit#(1)) wrgpioa_a1_in<-mkDWire(0);
 139       Wire#(Bit#(1)) wrgpioa_a2_out<-mkDWire(0);
 140       Wire#(Bit#(1)) wrgpioa_a2_outen<-mkDWire(0);
 141       Wire#(Bit#(1)) wrgpioa_a2_in<-mkDWire(0);
 142
 143       // following wires capture signals to IO CELL if twi-0 is
 144       // allotted to it
 145       Wire#(Bit#(1)) wrtwi_sda_out<-mkDWire(0);
 146       Wire#(Bit#(1)) wrtwi_sda_outen<-mkDWire(0);
 147       Wire#(Bit#(1)) wrtwi_sda_in<-mkDWire(0);
 148       Wire#(Bit#(1)) wrtwi_scl_out<-mkDWire(0);
 149       Wire#(Bit#(1)) wrtwi_scl_outen<-mkDWire(0);
 150       Wire#(Bit#(1)) wrtwi_scl_in<-mkDWire(0);
 151
 152
 153       /*====== This where the muxing starts for each io-cell======*/
 154        // output muxer for cell idx 0
 155       cell0_mux_out=
 156                         wrcell0_mux==0?wrgpioa_a0_out:
 157                         wrcell0_mux==1?wruart_tx_out:
 158                         wrcell0_mux==2?0: // unused
 159                         0; // unused
 160
 161       // outen muxer for cell idx 0
 162       cell0_mux_outen=
 163                         wrcell0_mux==0?wrgpioa_a0_outen: // bi-directional
 164                         wrcell0_mux==1?1: // uart_tx is an output
 165                         wrcell0_mux==2?0: // unused
 166                         0; // unused
 167
 168       rule assign_wrgpioa_a0_in_on_cell0(wrcell0_mux==0);
 169         wrgpioa_a0_in<=cell0_mux_in;
 170       endrule
 171
 172       // output muxer for cell idx 1
 173       cell1_mux_out=
 174                         wrcell1_mux==0?wrgpioa_a1_out:
 175                         wrcell1_mux==1?0: // uart_rx is an input
 176                         wrcell1_mux==2?wrtwi_sda_out:
 177                         0; // unused
 178
 179       // outen muxer for cell idx 1
 180       cell1_mux_outen=
 181                         wrcell1_mux==0?wrgpioa_a1_outen: // bi-directional
 182                         wrcell1_mux==1?0: // uart_rx is an input
 183                         wrcell1_mux==2?wrtwi_sda_outen: // bi-directional
 184                         0; // unused
 185
 186       rule assign_wrgpioa_a1_in_on_cell1(wrcell1_mux==0);
 187         wrgpioa_a1_in<=cell1_mux_in;
 188       endrule
 189
 190
 191       rule assign_wruart_rx_on_cell1(wrcell1_mux==1);
 192         wruart_rx<=cell1_mux_in;
 193       endrule
 194
 195
 196       rule assign_wrtwi_sda_in_on_cell1(wrcell1_mux==2);
 197         wrtwi_sda_in<=cell1_mux_in;
 198       endrule
 199
 200       // output muxer for cell idx 2
 201       cell2_mux_out=
 202                         wrcell2_mux==0?wrgpioa_a2_out:
 203                         wrcell2_mux==1?0: // unused
 204                         wrcell2_mux==2?wrtwi_scl_out:
 205                         0; // unused
 206
 207       // outen muxer for cell idx 2
 208       cell2_mux_outen=
 209                         wrcell2_mux==0?wrgpioa_a2_outen: // bi-directional
 210                         wrcell2_mux==1?0: // unused
 211                         wrcell2_mux==2?wrtwi_scl_outen: // bi-directional
 212                         0; // unused
 213
 214       rule assign_wrgpioa_a2_in_on_cell2(wrcell2_mux==0);
 215         wrgpioa_a2_in<=cell2_mux_in;
 216       endrule
 217
 218
 219       rule assign_wrtwi_scl_in_on_cell2(wrcell2_mux==2);
 220         wrtwi_scl_in<=cell2_mux_in;
 221       endrule
 222
 223
 224       /*============================================================*/
 225
 226     interface mux_lines = interface MuxSelectionLines
 227
 228       method Action  cell0_mux(Bit#(2) in);
 229          wrcell0_mux<=in;
 230       endmethod
 231
 232       method Action  cell1_mux(Bit#(2) in);
 233          wrcell1_mux<=in;
 234       endmethod
 235
 236       method Action  cell2_mux(Bit#(2) in);
 237          wrcell2_mux<=in;
 238       endmethod
 239
 240     endinterface;
 241     interface iocell_side = interface IOCellSide
 242
 243       method io0_cell_out=cell0_mux_out;
 244       method io0_cell_outen=cell0_mux_outen;
 245       method Action  io0_cell_in(Bit#(1) in);
 246          cell0_mux_in<=in;
 247       endmethod
 248
 249       method io1_cell_out=cell1_mux_out;
 250       method io1_cell_outen=cell1_mux_outen;
 251       method Action  io1_cell_in(Bit#(1) in);
 252          cell1_mux_in<=in;
 253       endmethod
 254
 255       method io2_cell_out=cell2_mux_out;
 256       method io2_cell_outen=cell2_mux_outen;
 257       method Action  io2_cell_in(Bit#(1) in);
 258          cell2_mux_in<=in;
 259       endmethod
 260
 261      endinterface;
 262     interface peripheral_side = interface PeripheralSide
 263
 264       method Action  uart_tx(Bit#(1) in);
 265          wruart_tx<=in;
 266       endmethod
 267       method uart_rx=wruart_rx;
 268
 269       method Action  gpioa_a0_out(Bit#(1) in);
 270          wrgpioa_a0_out<=in;
 271       endmethod
 272       method Action  gpioa_a0_outen(Bit#(1) in);
 273          wrgpioa_a0_outen<=in;
 274       endmethod
 275       method gpioa_a0_in=wrgpioa_a0_in;
 276       method Action  gpioa_a1_out(Bit#(1) in);
 277          wrgpioa_a1_out<=in;
 278       endmethod
 279       method Action  gpioa_a1_outen(Bit#(1) in);
 280          wrgpioa_a1_outen<=in;
 281       endmethod
 282       method gpioa_a1_in=wrgpioa_a1_in;
 283       method Action  gpioa_a2_out(Bit#(1) in);
 284          wrgpioa_a2_out<=in;
 285       endmethod
 286       method Action  gpioa_a2_outen(Bit#(1) in);
 287          wrgpioa_a2_outen<=in;
 288       endmethod
 289       method gpioa_a2_in=wrgpioa_a2_in;
 290
 291       method Action  twi_sda_out(Bit#(1) in);
 292          wrtwi_sda_out<=in;
 293       endmethod
 294       method Action  twi_sda_outen(Bit#(1) in);
 295          wrtwi_sda_outen<=in;
 296       endmethod
 297       method twi_sda_in=wrtwi_sda_in;
 298       method Action  twi_scl_out(Bit#(1) in);
 299          wrtwi_scl_out<=in;
 300       endmethod
 301       method Action  twi_scl_outen(Bit#(1) in);
 302          wrtwi_scl_outen<=in;
 303       endmethod
 304       method twi_scl_in=wrtwi_scl_in;
 305
 306      endinterface;
 307    endmodule
 308 endpackage