src/test_bsv/pinmux.bsv

   1
   2 /*
   3    This BSV file has been generated by the PinMux tool available at:
   4    https://bitbucket.org/casl/pinmux.
   5
   6    Authors: Neel Gala, Luke
   7    Date of generation: Sun Jun 24 12:09:36 2018
   8 */
   9
  10 package pinmux;
  11
  12    interface MuxSelectionLines;
  13
  14       // declare the method which will capture the user pin-mux
  15       // selection values.The width of the input is dependent on the number
  16       // of muxes happening per IO. For now we have a generalized width
  17       // where each IO will have the same number of muxes.
  18      method  Action cell0_mux (Bit#(2) in);
  19      method  Action cell1_mux (Bit#(2) in);
  20      method  Action cell2_mux (Bit#(2) in);
  21       endinterface
  22
  23       interface PeripheralSide;
  24       // declare the interface to the IO cells.
  25       // Each IO cell will have 8 input field (output from pin mux
  26       // and on output field (input to pinmux)
  27           // interface declaration between IO-0 and pinmux
  28     (*always_ready,always_enabled*) method  Bit#(1) io0_cell_out;
  29     (*always_ready,always_enabled*) method  Bit#(1) io0_cell_outen;
  30     (*always_ready,always_enabled,result="io"*) method
  31                        Action io0_inputval (Bit#(1) in);
  32           // interface declaration between IO-1 and pinmux
  33     (*always_ready,always_enabled*) method  Bit#(1) io1_cell_out;
  34     (*always_ready,always_enabled*) method  Bit#(1) io1_cell_outen;
  35     (*always_ready,always_enabled,result="io"*) method
  36                        Action io1_inputval (Bit#(1) in);
  37           // interface declaration between IO-2 and pinmux
  38     (*always_ready,always_enabled*) method  Bit#(1) io2_cell_out;
  39     (*always_ready,always_enabled*) method  Bit#(1) io2_cell_outen;
  40     (*always_ready,always_enabled,result="io"*) method
  41                        Action io2_inputval (Bit#(1) in);
  42           // interface declaration between UART-0 and pinmux
  43     (*always_ready,always_enabled*) method  Action uart_tx (Bit#(1) in);
  44     (*always_ready,always_enabled*) method  Bit#(1) uart_rx;
  45           // interface declaration between GPIOA-0 and pinmux
  46     (*always_ready,always_enabled*) method  Action gpioa_a0_out (Bit#(1) in);
  47     (*always_ready,always_enabled*) method  Action gpioa_a0_outen (Bit#(1) in);
  48     (*always_ready,always_enabled*) method  Bit#(1) gpioa_a0_in;
  49     (*always_ready,always_enabled*) method  Action gpioa_a1_out (Bit#(1) in);
  50     (*always_ready,always_enabled*) method  Action gpioa_a1_outen (Bit#(1) in);
  51     (*always_ready,always_enabled*) method  Bit#(1) gpioa_a1_in;
  52     (*always_ready,always_enabled*) method  Action gpioa_a2_out (Bit#(1) in);
  53     (*always_ready,always_enabled*) method  Action gpioa_a2_outen (Bit#(1) in);
  54     (*always_ready,always_enabled*) method  Bit#(1) gpioa_a2_in;
  55           // interface declaration between TWI-0 and pinmux
  56     (*always_ready,always_enabled*) method  Action twi_sda_out (Bit#(1) in);
  57     (*always_ready,always_enabled*) method  Action twi_sda_outen (Bit#(1) in);
  58     (*always_ready,always_enabled*) method  Bit#(1) twi_sda_in;
  59     (*always_ready,always_enabled*) method  Action twi_scl_out (Bit#(1) in);
  60     (*always_ready,always_enabled*) method  Action twi_scl_outen (Bit#(1) in);
  61     (*always_ready,always_enabled*) method  Bit#(1) twi_scl_in;
  62    endinterface
  63
  64    interface Ifc_pinmux;
  65       interface MuxSelectionLines mux_lines;
  66       interface PeripheralSide peripheral_side;
  67    endinterface
  68    (*synthesize*)
  69    module mkpinmux(Ifc_pinmux);
  70
  71       // the followins wires capture the pin-mux selection
  72       // values for each mux assigned to a CELL
  73
  74       Wire#(Bit#(2)) wrcell0_mux<-mkDWire(0);
  75       Wire#(Bit#(2)) wrcell1_mux<-mkDWire(0);
  76       Wire#(Bit#(2)) wrcell2_mux<-mkDWire(0);
  77       // following wires capture signals to IO CELL if io-0 is
  78       // allotted to it
  79       Wire#(Bit#(1)) cell0_mux_out<-mkDWire(0);
  80       Wire#(Bit#(1)) cell0_mux_outen<-mkDWire(0);
  81       Wire#(Bit#(1)) cell0_mux_in<-mkDWire(0);
  82
  83       // following wires capture signals to IO CELL if io-1 is
  84       // allotted to it
  85       Wire#(Bit#(1)) cell1_mux_out<-mkDWire(0);
  86       Wire#(Bit#(1)) cell1_mux_outen<-mkDWire(0);
  87       Wire#(Bit#(1)) cell1_mux_in<-mkDWire(0);
  88
  89       // following wires capture signals to IO CELL if io-2 is
  90       // allotted to it
  91       Wire#(Bit#(1)) cell2_mux_out<-mkDWire(0);
  92       Wire#(Bit#(1)) cell2_mux_outen<-mkDWire(0);
  93       Wire#(Bit#(1)) cell2_mux_in<-mkDWire(0);
  94
  95       // following wires capture signals to IO CELL if uart-0 is
  96       // allotted to it
  97       Wire#(Bit#(1)) wruart_tx<-mkDWire(0);
  98       Wire#(Bit#(1)) wruart_rx<-mkDWire(0);
  99
 100       // following wires capture signals to IO CELL if gpioa-0 is
 101       // allotted to it
 102       Wire#(Bit#(1)) wrgpioa_a0_out<-mkDWire(0);
 103       Wire#(Bit#(1)) wrgpioa_a0_outen<-mkDWire(0);
 104       Wire#(Bit#(1)) wrgpioa_a0_in<-mkDWire(0);
 105       Wire#(Bit#(1)) wrgpioa_a1_out<-mkDWire(0);
 106       Wire#(Bit#(1)) wrgpioa_a1_outen<-mkDWire(0);
 107       Wire#(Bit#(1)) wrgpioa_a1_in<-mkDWire(0);
 108       Wire#(Bit#(1)) wrgpioa_a2_out<-mkDWire(0);
 109       Wire#(Bit#(1)) wrgpioa_a2_outen<-mkDWire(0);
 110       Wire#(Bit#(1)) wrgpioa_a2_in<-mkDWire(0);
 111
 112       // following wires capture signals to IO CELL if twi-0 is
 113       // allotted to it
 114       Wire#(Bit#(1)) wrtwi_sda_out<-mkDWire(0);
 115       Wire#(Bit#(1)) wrtwi_sda_outen<-mkDWire(0);
 116       Wire#(Bit#(1)) wrtwi_sda_in<-mkDWire(0);
 117       Wire#(Bit#(1)) wrtwi_scl_out<-mkDWire(0);
 118       Wire#(Bit#(1)) wrtwi_scl_outen<-mkDWire(0);
 119       Wire#(Bit#(1)) wrtwi_scl_in<-mkDWire(0);
 120
 121
 122       /*====== This where the muxing starts for each io-cell======*/
 123        // output muxer for cell idx 0
 124       cell0_mux_out=
 125                         wrcell0_mux==0?wrgpioa_a0_out:
 126                         wrcell0_mux==1?wruart_tx_out:
 127                         wrcell0_mux==2?0: // unused
 128                         0; // unused
 129
 130       // outen muxer for cell idx 0
 131       cell0_mux_outen=
 132                         wrcell0_mux==0?wrgpioa_a0_outen: // bi-directional
 133                         wrcell0_mux==1?1: // uart_tx is an output
 134                         wrcell0_mux==2?0: // unused
 135                         0; // unused
 136
 137       rule assign_wrgpioa_a0_in_on_cell0(wrcell0_mux==0);
 138         wrgpioa_a0_in<=cell0_mux_in;
 139       endrule
 140
 141       // output muxer for cell idx 1
 142       cell1_mux_out=
 143                         wrcell1_mux==0?wrgpioa_a1_out:
 144                         wrcell1_mux==1?0: // uart_rx is an input
 145                         wrcell1_mux==2?wrtwi_sda_out:
 146                         0; // unused
 147
 148       // outen muxer for cell idx 1
 149       cell1_mux_outen=
 150                         wrcell1_mux==0?wrgpioa_a1_outen: // bi-directional
 151                         wrcell1_mux==1?0: // uart_rx is an input
 152                         wrcell1_mux==2?wrtwi_sda_outen: // bi-directional
 153                         0; // unused
 154
 155       rule assign_wrgpioa_a1_in_on_cell1(wrcell1_mux==0);
 156         wrgpioa_a1_in<=cell1_mux_in;
 157       endrule
 158
 159
 160       rule assign_wruart_rx_on_cell1(wrcell1_mux==1);
 161         wruart_rx<=cell1_mux_in;
 162       endrule
 163
 164
 165       rule assign_wrtwi_sda_in_on_cell1(wrcell1_mux==2);
 166         wrtwi_sda_in<=cell1_mux_in;
 167       endrule
 168
 169       // output muxer for cell idx 2
 170       cell2_mux_out=
 171                         wrcell2_mux==0?wrgpioa_a2_out:
 172                         wrcell2_mux==1?0: // unused
 173                         wrcell2_mux==2?wrtwi_scl_out:
 174                         0; // unused
 175
 176       // outen muxer for cell idx 2
 177       cell2_mux_outen=
 178                         wrcell2_mux==0?wrgpioa_a2_outen: // bi-directional
 179                         wrcell2_mux==1?0: // unused
 180                         wrcell2_mux==2?wrtwi_scl_outen: // bi-directional
 181                         0; // unused
 182
 183       rule assign_wrgpioa_a2_in_on_cell2(wrcell2_mux==0);
 184         wrgpioa_a2_in<=cell2_mux_in;
 185       endrule
 186
 187
 188       rule assign_wrtwi_scl_in_on_cell2(wrcell2_mux==2);
 189         wrtwi_scl_in<=cell2_mux_in;
 190       endrule
 191
 192
 193       /*============================================================*/
 194
 195     interface mux_lines = interface MuxSelectionLines
 196
 197       method Action  cell0_mux(Bit#(2) in);
 198          wrcell0_mux<=in;
 199       endmethod
 200
 201       method Action  cell1_mux(Bit#(2) in);
 202          wrcell1_mux<=in;
 203       endmethod
 204
 205       method Action  cell2_mux(Bit#(2) in);
 206          wrcell2_mux<=in;
 207       endmethod
 208
 209     endinterface;
 210     interface peripheral_side = interface PeripheralSide
 211
 212       method io0_cell_out=cell0_mux_out;
 213       method io0_cell_outen=cell0_mux_outen;
 214       method Action  io0_inputval(Bit#(1) in);
 215          cell0_mux_in<=in;
 216       endmethod
 217
 218       method io1_cell_out=cell1_mux_out;
 219       method io1_cell_outen=cell1_mux_outen;
 220       method Action  io1_inputval(Bit#(1) in);
 221          cell1_mux_in<=in;
 222       endmethod
 223
 224       method io2_cell_out=cell2_mux_out;
 225       method io2_cell_outen=cell2_mux_outen;
 226       method Action  io2_inputval(Bit#(1) in);
 227          cell2_mux_in<=in;
 228       endmethod
 229
 230       method Action  uart_tx(Bit#(1) in);
 231          wruart_tx<=in;
 232       endmethod
 233       method uart_rx=wruart_rx;
 234
 235       method Action  gpioa_a0_out(Bit#(1) in);
 236          wrgpioa_a0_out<=in;
 237       endmethod
 238       method Action  gpioa_a0_outen(Bit#(1) in);
 239          wrgpioa_a0_outen<=in;
 240       endmethod
 241       method gpioa_a0_in=wrgpioa_a0_in;
 242       method Action  gpioa_a1_out(Bit#(1) in);
 243          wrgpioa_a1_out<=in;
 244       endmethod
 245       method Action  gpioa_a1_outen(Bit#(1) in);
 246          wrgpioa_a1_outen<=in;
 247       endmethod
 248       method gpioa_a1_in=wrgpioa_a1_in;
 249       method Action  gpioa_a2_out(Bit#(1) in);
 250          wrgpioa_a2_out<=in;
 251       endmethod
 252       method Action  gpioa_a2_outen(Bit#(1) in);
 253          wrgpioa_a2_outen<=in;
 254       endmethod
 255       method gpioa_a2_in=wrgpioa_a2_in;
 256
 257       method Action  twi_sda_out(Bit#(1) in);
 258          wrtwi_sda_out<=in;
 259       endmethod
 260       method Action  twi_sda_outen(Bit#(1) in);
 261          wrtwi_sda_outen<=in;
 262       endmethod
 263       method twi_sda_in=wrtwi_sda_in;
 264       method Action  twi_scl_out(Bit#(1) in);
 265          wrtwi_scl_out<=in;
 266       endmethod
 267       method Action  twi_scl_outen(Bit#(1) in);
 268          wrtwi_scl_outen<=in;
 269       endmethod
 270       method twi_scl_in=wrtwi_scl_in;
 271
 272      endinterface;
 273    endmodule
 274 endpackage