src/test_bsv/pinmux_experiment.bsv

   1
   2 /*
   3    This BSV file has been generated by the PinMux tool available at:
   4    https://bitbucket.org/casl/pinmux.
   5
   6    Authors: Neel Gala, Luke
   7    Date of generation: Sun Jul 22 05:31:10 2018
   8 */
   9
  10 package pinmux_experiment;
  11
  12 import GetPut::*;
  13
  14       (*always_ready,always_enabled*)
  15    interface MuxSelectionLines;
  16
  17       // declare the method which will capture the user pin-mux
  18       // selection values.The width of the input is dependent on the number
  19       // of muxes happening per IO. For now we have a generalized width
  20       // where each IO will have the same number of muxes.
  21      method  Action cell0_mux (Bit#(2) in);
  22      method  Action cell1_mux (Bit#(2) in);
  23      method  Action cell2_mux (Bit#(2) in);
  24       endinterface
  25
  26
  27       interface IOCellSide;
  28       // declare the interface to the IO cells.
  29       // Each IO cell will have 1 input field (output from pin mux)
  30       // and an output and out-enable field (input to pinmux)
  31           // interface declaration between IO-0 and pinmux
  32     (*always_ready,always_enabled*) method  Bit#(1) io0_cell_out;
  33     (*always_ready,always_enabled*) method  Bit#(1) io0_cell_outen;
  34     (*always_ready,always_enabled,result="io"*) method
  35                        Action io0_cell_in (Bit#(1) in);
  36           // interface declaration between IO-1 and pinmux
  37     (*always_ready,always_enabled*) method  Bit#(1) io1_cell_out;
  38     (*always_ready,always_enabled*) method  Bit#(1) io1_cell_outen;
  39     (*always_ready,always_enabled,result="io"*) method
  40                        Action io1_cell_in (Bit#(1) in);
  41           // interface declaration between IO-2 and pinmux
  42     (*always_ready,always_enabled*) method  Bit#(1) io2_cell_out;
  43     (*always_ready,always_enabled*) method  Bit#(1) io2_cell_outen;
  44     (*always_ready,always_enabled,result="io"*) method
  45                        Action io2_cell_in (Bit#(1) in);
  46       endinterface
  47
  48
  49       (*always_ready,always_enabled*)
  50       interface PeripheralSideUART;
  51           // interface declaration between UART and pinmux
  52           interface Put#(Bit#(1)) tx;
  53           interface Get#(Bit#(1)) rx;
  54 //    (*always_ready,always_enabled*) method  Action tx (Bit#(1) in);
  55 //    (*always_ready,always_enabled*) method  Bit#(1) rx;
  56       endinterface
  57
  58       (*always_ready,always_enabled*)
  59       interface PeripheralSideGPIOA;
  60           // interface declaration between GPIOA-0 and pinmux
  61           interface Put#(Bit#(1)) a0_out;
  62           interface Put#(Bit#(1)) a0_outen;
  63           interface Get#(Bit#(1)) a0_in;
  64           interface Put#(Bit#(1)) a1_out;
  65           interface Put#(Bit#(1)) a1_outen;
  66           interface Get#(Bit#(1)) a1_in;
  67           interface Put#(Bit#(1)) a2_out;
  68           interface Put#(Bit#(1)) a2_outen;
  69           interface Get#(Bit#(1)) a2_in;
  70         endinterface
  71
  72       (*always_ready,always_enabled*)
  73       interface PeripheralSideTWI;
  74           // interface declaration between TWI and pinmux
  75           interface Put#(Bit#(1)) sda_out;
  76           interface Put#(Bit#(1)) sda_outen;
  77           interface Get#(Bit#(1)) sda_in;
  78           interface Put#(Bit#(1)) scl_out;
  79           interface Put#(Bit#(1)) scl_outen;
  80           interface Get#(Bit#(1)) scl_in;
  81       endinterface
  82
  83       (*always_ready,always_enabled*)
  84       interface PeripheralSide;
  85       // declare the interface to the peripherals
  86       // Each peripheral's function will be either an input, output
  87       // or be bi-directional.  an input field will be an output from the
  88       // peripheral and an output field will be an input to the peripheral.
  89       // Bi-directional functions also have an output-enable (which
  90       // again comes *in* from the peripheral)
  91           // interface declaration between UART-0 and pinmux
  92             interface PeripheralSideUART uart;
  93             interface PeripheralSideGPIOA gpioa;
  94             interface PeripheralSideTWI twi;
  95       endinterface
  96
  97
  98    interface Ifc_pinmux;
  99       // this interface controls how each IO cell is routed.  setting
 100       // any given IO cell's mux control value will result in redirection
 101       // of not just the input or output to different peripheral functions
 102       // but also the *direction* control - if appropriate - as well.
 103       interface MuxSelectionLines mux_lines;
 104
 105       // this interface contains the inputs, outputs and direction-control
 106       // lines for all peripherals.  GPIO is considered to also be just
 107       // a peripheral because it also has in, out and direction-control.
 108       interface PeripheralSide peripheral_side;
 109
 110       // this interface is to be linked to the individual IO cells.
 111       // if looking at a "non-muxed" GPIO design, basically the
 112       // IO cell input, output and direction-control wires are cut
 113       // (giving six pairs of dangling wires, named left and right)
 114       // these iocells are routed in their place on one side ("left")
 115       // and the matching *GPIO* peripheral interfaces in/out/dir
 116       // connect to the OTHER side ("right").  the result is that
 117       // the muxer settings end up controlling the routing of where
 118       // the I/O from the IOcell actually goes.
 119       interface IOCellSide iocell_side;
 120    endinterface
 121    (*synthesize*)
 122
 123    module mkpinmux(Ifc_pinmux);
 124
 125       // the followins wires capture the pin-mux selection
 126       // values for each mux assigned to a CELL
 127
 128       Wire#(Bit#(2)) wrcell0_mux<-mkDWire(0);
 129       Wire#(Bit#(2)) wrcell1_mux<-mkDWire(0);
 130       Wire#(Bit#(2)) wrcell2_mux<-mkDWire(0);
 131       // following wires capture signals to IO CELL if io-0 is
 132       // allotted to it
 133       Wire#(Bit#(1)) cell0_mux_out<-mkDWire(0);
 134       Wire#(Bit#(1)) cell0_mux_outen<-mkDWire(0);
 135       Wire#(Bit#(1)) cell0_mux_in<-mkDWire(0);
 136
 137       // following wires capture signals to IO CELL if io-1 is
 138       // allotted to it
 139       Wire#(Bit#(1)) cell1_mux_out<-mkDWire(0);
 140       Wire#(Bit#(1)) cell1_mux_outen<-mkDWire(0);
 141       Wire#(Bit#(1)) cell1_mux_in<-mkDWire(0);
 142
 143       // following wires capture signals to IO CELL if io-2 is
 144       // allotted to it
 145       Wire#(Bit#(1)) cell2_mux_out<-mkDWire(0);
 146       Wire#(Bit#(1)) cell2_mux_outen<-mkDWire(0);
 147       Wire#(Bit#(1)) cell2_mux_in<-mkDWire(0);
 148
 149       // following wires capture signals to IO CELL if uart-0 is
 150       // allotted to it
 151       Wire#(Bit#(1)) wruart_tx<-mkDWire(0);
 152       Wire#(Bit#(1)) wruart_rx<-mkDWire(0);
 153
 154       // following wires capture signals to IO CELL if gpioa-0 is
 155       // allotted to it
 156       Wire#(Bit#(1)) wrgpioa_a0_out<-mkDWire(0);
 157       Wire#(Bit#(1)) wrgpioa_a0_outen<-mkDWire(0);
 158       Wire#(Bit#(1)) wrgpioa_a0_in<-mkDWire(0);
 159       Wire#(Bit#(1)) wrgpioa_a1_out<-mkDWire(0);
 160       Wire#(Bit#(1)) wrgpioa_a1_outen<-mkDWire(0);
 161       Wire#(Bit#(1)) wrgpioa_a1_in<-mkDWire(0);
 162       Wire#(Bit#(1)) wrgpioa_a2_out<-mkDWire(0);
 163       Wire#(Bit#(1)) wrgpioa_a2_outen<-mkDWire(0);
 164       Wire#(Bit#(1)) wrgpioa_a2_in<-mkDWire(0);
 165
 166       // following wires capture signals to IO CELL if twi-0 is
 167       // allotted to it
 168       Wire#(Bit#(1)) wrtwi_sda_out<-mkDWire(0);
 169       Wire#(Bit#(1)) wrtwi_sda_outen<-mkDWire(0);
 170       Wire#(Bit#(1)) wrtwi_sda_in<-mkDWire(0);
 171       Wire#(Bit#(1)) wrtwi_scl_out<-mkDWire(0);
 172       Wire#(Bit#(1)) wrtwi_scl_outen<-mkDWire(0);
 173       Wire#(Bit#(1)) wrtwi_scl_in<-mkDWire(0);
 174
 175
 176       /*====== This where the muxing starts for each io-cell======*/
 177       Wire#(Bit#(1)) val0<-mkDWire(0); // need a zero
 178        // output muxer for cell idx 0
 179       cell0_mux_out=
 180                         wrcell0_mux==0?wrgpioa_a0_out:
 181                         wrcell0_mux==1?wruart_tx:
 182                         wrcell0_mux==2?val0: // unused
 183                         wrtwi_sda_out;
 184
 185       // outen muxer for cell idx 0
 186       cell0_mux_outen=
 187                         wrcell0_mux==0?wrgpioa_a0_outen: // bi-directional
 188                         wrcell0_mux==1?wrgpioa_a0_outen: // uart_tx is an output
 189                         wrcell0_mux==2?val0: // unused
 190                         wrtwi_sda_outen; // bi-directional
 191
 192       // priority-in-muxer for cell idx 0
 193       rule assign_wrgpioa_a0_in_on_cell0(wrcell0_mux==0);
 194         wrgpioa_a0_in<=cell0_mux_in;
 195       endrule
 196
 197       rule assign_wrtwi_sda_in_on_cell0(wrcell0_mux==3);
 198         wrtwi_sda_in<=cell0_mux_in;
 199       endrule
 200
 201       // output muxer for cell idx 1
 202       cell1_mux_out=
 203                         wrcell1_mux==0?wrgpioa_a1_out:
 204                         wrcell1_mux==1?val0: // uart_rx is an input
 205                         wrcell1_mux==2?wrtwi_sda_out:
 206                         val0; // unused
 207
 208       // outen muxer for cell idx 1
 209       cell1_mux_outen=
 210                         wrcell1_mux==0?wrgpioa_a1_outen: // bi-directional
 211                         wrcell1_mux==1?val0: // uart_rx is an input
 212                         wrcell1_mux==2?wrtwi_sda_outen: // bi-directional
 213                         val0; // unused
 214
 215       // priority-in-muxer for cell idx 1
 216       rule assign_wrgpioa_a1_in_on_cell1(wrcell1_mux==0);
 217         wrgpioa_a1_in<=cell1_mux_in;
 218       endrule
 219
 220       rule assign_wruart_rx_on_cell1(wrcell1_mux==1);
 221         wruart_rx<=cell1_mux_in;
 222       endrule
 223
 224       rule assign_wrtwi_sda_in_on_cell1(wrcell1_mux==2);
 225         wrtwi_sda_in<=cell1_mux_in;
 226       endrule
 227
 228       // output muxer for cell idx 2
 229       cell2_mux_out=
 230                         wrcell2_mux==0?wrgpioa_a2_out:
 231                         wrcell2_mux==1?val0: // unused
 232                         wrcell2_mux==2?wrtwi_scl_out:
 233                         val0; // unused
 234
 235       // outen muxer for cell idx 2
 236       cell2_mux_outen=
 237                         wrcell2_mux==0?wrgpioa_a2_outen: // bi-directional
 238                         wrcell2_mux==1?val0: // unused
 239                         wrcell2_mux==2?wrtwi_scl_outen: // bi-directional
 240                         val0; // unused
 241
 242       // priority-in-muxer for cell idx 2
 243       rule assign_wrgpioa_a2_in_on_cell2(wrcell2_mux==0);
 244         wrgpioa_a2_in<=cell2_mux_in;
 245       endrule
 246
 247       rule assign_wrtwi_scl_in_on_cell2(wrcell2_mux==2);
 248         wrtwi_scl_in<=cell2_mux_in;
 249       endrule
 250
 251
 252       /*=========================================*/
 253       // dedicated cells
 254
 255
 256       /*============================================================*/
 257
 258     interface mux_lines = interface MuxSelectionLines
 259
 260       method Action  cell0_mux(Bit#(2) in);
 261          wrcell0_mux<=in;
 262       endmethod
 263
 264       method Action  cell1_mux(Bit#(2) in);
 265          wrcell1_mux<=in;
 266       endmethod
 267
 268       method Action  cell2_mux(Bit#(2) in);
 269          wrcell2_mux<=in;
 270       endmethod
 271
 272     endinterface;
 273
 274     interface iocell_side = interface IOCellSide
 275
 276       method io0_cell_out=cell0_mux_out;
 277       method io0_cell_outen=cell0_mux_outen;
 278       method Action  io0_cell_in(Bit#(1) in);
 279          cell0_mux_in<=in;
 280       endmethod
 281
 282       method io1_cell_out=cell1_mux_out;
 283       method io1_cell_outen=cell1_mux_outen;
 284       method Action  io1_cell_in(Bit#(1) in);
 285          cell1_mux_in<=in;
 286       endmethod
 287
 288       method io2_cell_out=cell2_mux_out;
 289       method io2_cell_outen=cell2_mux_outen;
 290       method Action  io2_cell_in(Bit#(1) in);
 291          cell2_mux_in<=in;
 292       endmethod
 293
 294      endinterface;
 295       interface peripheral_side= interface PeripheralSide
 296         interface uart = interface PeripheralSideUART
 297             // interface declaration between UART and pinmux
 298             interface tx = interface Put
 299               method Action put(Bit#(1) in);
 300                 wruart_tx<=in;
 301               endmethod
 302             endinterface;
 303             interface  rx = interface Get
 304               method ActionValue#(Bit#(1)) get;
 305                 return wruart_rx;
 306               endmethod
 307             endinterface;
 308         endinterface;
 309
 310         interface twi = interface PeripheralSideTWI
 311             // interface declaration between TWI and pinmux
 312             interface sda_out = interface Put
 313               method Action put(Bit#(1) in);
 314                 wrtwi_sda_out<=in;
 315               endmethod
 316             endinterface;
 317             interface sda_outen = interface Put
 318               method Action put(Bit#(1) in);
 319                 wrtwi_sda_outen<=in;
 320               endmethod
 321             endinterface;
 322             interface  sda_in = interface Get
 323               method ActionValue#(Bit#(1)) get;
 324                 return wrtwi_sda_in;
 325               endmethod
 326             endinterface;
 327             interface scl_out = interface Put
 328               method Action put(Bit#(1) in);
 329                 wrtwi_scl_out<=in;
 330               endmethod
 331             endinterface;
 332             interface scl_outen = interface Put
 333               method Action put(Bit#(1) in);
 334                 wrtwi_scl_outen<=in;
 335               endmethod
 336             endinterface;
 337             interface  scl_in = interface Get
 338               method ActionValue#(Bit#(1)) get;
 339                 return wrtwi_scl_in;
 340               endmethod
 341             endinterface;
 342          endinterface;
 343
 344         interface gpioa = interface PeripheralSideGPIOA
 345
 346             interface a0_out = interface Put
 347               method Action put(Bit#(1) in);
 348                 wrgpioa_a0_out<=in;
 349               endmethod
 350             endinterface;
 351             interface a0_outen = interface Put
 352               method Action put(Bit#(1) in);
 353                 wrgpioa_a0_outen<=in;
 354               endmethod
 355             endinterface;
 356             interface  a0_in = interface Get
 357               method ActionValue#(Bit#(1)) get;
 358                 return wrgpioa_a0_in;
 359               endmethod
 360             endinterface;
 361             interface a1_out = interface Put
 362               method Action put(Bit#(1) in);
 363                 wrgpioa_a1_out<=in;
 364               endmethod
 365             endinterface;
 366             interface a1_outen = interface Put
 367               method Action put(Bit#(1) in);
 368                 wrgpioa_a1_outen<=in;
 369               endmethod
 370             endinterface;
 371             interface  a1_in = interface Get
 372               method ActionValue#(Bit#(1)) get;
 373                 return wrgpioa_a1_in;
 374               endmethod
 375             endinterface;
 376             interface a2_out = interface Put
 377               method Action put(Bit#(1) in);
 378                 wrgpioa_a2_out<=in;
 379               endmethod
 380             endinterface;
 381             interface a2_outen = interface Put
 382               method Action put(Bit#(1) in);
 383                 wrgpioa_a2_outen<=in;
 384               endmethod
 385             endinterface;
 386             interface  a2_in = interface Get
 387               method ActionValue#(Bit#(1)) get;
 388                 return wrgpioa_a2_in;
 389               endmethod
 390             endinterface;
 391         endinterface;
 392
 393
 394       endinterface;
 395 //    interface peripheral_side = interface PeripheralSide
 396 //
 397 //      interface uart = peripherals.uart;
 398 //      interface gpioa = peripherals.gpioa;
 399 //      interface twi = peripherals.twi;
 400 //
 401 //     endinterface;
 402    endmodule
 403 endpackage