3 This BSV file has been generated by the PinMux tool available at:
4 https://bitbucket.org/casl/pinmux.
6 Authors: Neel Gala, Luke
7 Date of generation: Sun Jul 22 05:31:10 2018
10 package pinmux_experiment;
12 interface MuxSelectionLines;
14 // declare the method which will capture the user pin-mux
15 // selection values.The width of the input is dependent on the number
16 // of muxes happening per IO. For now we have a generalized width
17 // where each IO will have the same number of muxes.
18 method Action cell0_mux (Bit#(2) in);
19 method Action cell1_mux (Bit#(2) in);
20 method Action cell2_mux (Bit#(2) in);
25 // declare the interface to the IO cells.
26 // Each IO cell will have 1 input field (output from pin mux)
27 // and an output and out-enable field (input to pinmux)
28 // interface declaration between IO-0 and pinmux
29 (*always_ready,always_enabled*) method Bit#(1) io0_cell_out;
30 (*always_ready,always_enabled*) method Bit#(1) io0_cell_outen;
31 (*always_ready,always_enabled,result="io"*) method
32 Action io0_cell_in (Bit#(1) in);
33 // interface declaration between IO-1 and pinmux
34 (*always_ready,always_enabled*) method Bit#(1) io1_cell_out;
35 (*always_ready,always_enabled*) method Bit#(1) io1_cell_outen;
36 (*always_ready,always_enabled,result="io"*) method
37 Action io1_cell_in (Bit#(1) in);
38 // interface declaration between IO-2 and pinmux
39 (*always_ready,always_enabled*) method Bit#(1) io2_cell_out;
40 (*always_ready,always_enabled*) method Bit#(1) io2_cell_outen;
41 (*always_ready,always_enabled,result="io"*) method
42 Action io2_cell_in (Bit#(1) in);
46 interface PeripheralSideUART;
47 // interface declaration between UART and pinmux
48 interface Put#(Bit#(1)) tx;
49 interface Get#(Bit#(1)) rx;
50 // (*always_ready,always_enabled*) method Action tx (Bit#(1) in);
51 // (*always_ready,always_enabled*) method Bit#(1) rx;
54 interface PeripheralSideGPIOA;
55 // interface declaration between GPIOA-0 and pinmux
56 (*always_ready,always_enabled*) method Action a0_out (Bit#(1) in);
57 (*always_ready,always_enabled*) method Action a0_outen (Bit#(1) in);
58 (*always_ready,always_enabled*) method Bit#(1) a0_in;
59 (*always_ready,always_enabled*) method Action a1_out (Bit#(1) in);
60 (*always_ready,always_enabled*) method Action a1_outen (Bit#(1) in);
61 (*always_ready,always_enabled*) method Bit#(1) a1_in;
62 (*always_ready,always_enabled*) method Action a2_out (Bit#(1) in);
63 (*always_ready,always_enabled*) method Action a2_outen (Bit#(1) in);
64 (*always_ready,always_enabled*) method Bit#(1) a2_in;
67 interface PeripheralSideTWI;
68 // interface declaration between TWI and pinmux
69 (*always_ready,always_enabled*) method Action sda_out (Bit#(1) in);
70 (*always_ready,always_enabled*) method Action sda_outen (Bit#(1) in);
71 (*always_ready,always_enabled*) method Bit#(1) sda_in;
72 (*always_ready,always_enabled*) method Action scl_out (Bit#(1) in);
73 (*always_ready,always_enabled*) method Action scl_outen (Bit#(1) in);
74 (*always_ready,always_enabled*) method Bit#(1) scl_in;
77 interface PeripheralSide;
78 // declare the interface to the peripherals
79 // Each peripheral's function will be either an input, output
80 // or be bi-directional. an input field will be an output from the
81 // peripheral and an output field will be an input to the peripheral.
82 // Bi-directional functions also have an output-enable (which
83 // again comes *in* from the peripheral)
84 // interface declaration between UART-0 and pinmux
85 interface PeripheralSideUART uart;
86 interface PeripheralSideGPIOA gpioa;
87 interface PeripheralSideTWI twi;
92 // this interface controls how each IO cell is routed. setting
93 // any given IO cell's mux control value will result in redirection
94 // of not just the input or output to different peripheral functions
95 // but also the *direction* control - if appropriate - as well.
96 interface MuxSelectionLines mux_lines;
98 // this interface contains the inputs, outputs and direction-control
99 // lines for all peripherals. GPIO is considered to also be just
100 // a peripheral because it also has in, out and direction-control.
101 interface PeripheralSide peripheral_side;
103 // this interface is to be linked to the individual IO cells.
104 // if looking at a "non-muxed" GPIO design, basically the
105 // IO cell input, output and direction-control wires are cut
106 // (giving six pairs of dangling wires, named left and right)
107 // these iocells are routed in their place on one side ("left")
108 // and the matching *GPIO* peripheral interfaces in/out/dir
109 // connect to the OTHER side ("right"). the result is that
110 // the muxer settings end up controlling the routing of where
111 // the I/O from the IOcell actually goes.
112 interface IOCellSide iocell_side;
116 // module mkgpioa(PeripheralSideGPIOA);
119 // Wire#(Bit#(1)) wr_a0_out<-mkDWire(0);
120 // Wire#(Bit#(1)) wr_a0_outen<-mkDWire(0);
121 // Wire#(Bit#(1)) wr_a0_in<-mkDWire(0);
122 // Wire#(Bit#(1)) wr_a1_out<-mkDWire(0);
123 // Wire#(Bit#(1)) wr_a1_outen<-mkDWire(0);
124 // Wire#(Bit#(1)) wr_a1_in<-mkDWire(0);
125 // Wire#(Bit#(1)) wr_a2_out<-mkDWire(0);
126 // Wire#(Bit#(1)) wr_a2_outen<-mkDWire(0);
127 // Wire#(Bit#(1)) wr_a2_in<-mkDWire(0);
129 // interface out = interface PeripheralSideGPIOA
131 // method Action a0_out(Bit#(1) in);
134 // method Action a0_outen(Bit#(1) in);
137 // method a0_in=wr_a0_in;
138 // method Action a1_out(Bit#(1) in);
141 // method Action a1_outen(Bit#(1) in);
144 // method a1_in=wr_a1_in;
145 // method Action a2_out(Bit#(1) in);
148 // method Action a2_outen(Bit#(1) in);
151 // method a2_in=wr_a2_in;
156 // module mkuart(PeripheralSideUART);
158 // Wire#(Bit#(1)) wr_tx<-mkDWire(0);
159 // Wire#(Bit#(1)) wr_rx<-mkDWire(0);
161 // interface out = interface PeripheralSideUART
163 // method Action tx(Bit#(1) in);
172 // module mktwi(PeripheralSideTWI);
174 // // following wires capture signals to IO CELL if twi-0 is
176 // Wire#(Bit#(1)) wr_sda_out<-mkDWire(0);
177 // Wire#(Bit#(1)) wr_sda_outen<-mkDWire(0);
178 // Wire#(Bit#(1)) wr_sda_in<-mkDWire(0);
179 // Wire#(Bit#(1)) wr_scl_out<-mkDWire(0);
180 // Wire#(Bit#(1)) wr_scl_outen<-mkDWire(0);
181 // Wire#(Bit#(1)) wr_scl_in<-mkDWire(0);
184 // interface out = interface PeripheralSideTWI
186 // method Action sda_out(Bit#(1) in);
189 // method Action sda_outen(Bit#(1) in);
192 // method sda_in=wr_sda_in;
193 // method Action scl_out(Bit#(1) in);
196 // method Action scl_outen(Bit#(1) in);
199 // method scl_in=wr_scl_in;
206 // module mkperipherals(PeripheralSide);
208 // PeripheralSideUART uart = mkuart();
209 // PeripheralSideGPIOA gpioa = mkgpioa();
210 // PeripheralSideTWI twi = mktwi();
212 // interface out = interface PeripheralSide
214 // interface uart = uart.out;
215 // interface gpioa = gpioa.out;
216 // interface twi = twi.out;
222 module mkpinmux(Ifc_pinmux);
224 // the followins wires capture the pin-mux selection
225 // values for each mux assigned to a CELL
227 Wire#(Bit#(2)) wrcell0_mux<-mkDWire(0);
228 Wire#(Bit#(2)) wrcell1_mux<-mkDWire(0);
229 Wire#(Bit#(2)) wrcell2_mux<-mkDWire(0);
230 // following wires capture signals to IO CELL if io-0 is
232 Wire#(Bit#(1)) cell0_mux_out<-mkDWire(0);
233 Wire#(Bit#(1)) cell0_mux_outen<-mkDWire(0);
234 Wire#(Bit#(1)) cell0_mux_in<-mkDWire(0);
236 // following wires capture signals to IO CELL if io-1 is
238 Wire#(Bit#(1)) cell1_mux_out<-mkDWire(0);
239 Wire#(Bit#(1)) cell1_mux_outen<-mkDWire(0);
240 Wire#(Bit#(1)) cell1_mux_in<-mkDWire(0);
242 // following wires capture signals to IO CELL if io-2 is
244 Wire#(Bit#(1)) cell2_mux_out<-mkDWire(0);
245 Wire#(Bit#(1)) cell2_mux_outen<-mkDWire(0);
246 Wire#(Bit#(1)) cell2_mux_in<-mkDWire(0);
248 // following wires capture signals to IO CELL if uart-0 is
250 Wire#(Bit#(1)) wruart_tx<-mkDWire(0);
251 Wire#(Bit#(1)) wruart_rx<-mkDWire(0);
253 // following wires capture signals to IO CELL if gpioa-0 is
255 Wire#(Bit#(1)) wrgpioa_a0_out<-mkDWire(0);
256 Wire#(Bit#(1)) wrgpioa_a0_outen<-mkDWire(0);
257 Wire#(Bit#(1)) wrgpioa_a0_in<-mkDWire(0);
258 Wire#(Bit#(1)) wrgpioa_a1_out<-mkDWire(0);
259 Wire#(Bit#(1)) wrgpioa_a1_outen<-mkDWire(0);
260 Wire#(Bit#(1)) wrgpioa_a1_in<-mkDWire(0);
261 Wire#(Bit#(1)) wrgpioa_a2_out<-mkDWire(0);
262 Wire#(Bit#(1)) wrgpioa_a2_outen<-mkDWire(0);
263 Wire#(Bit#(1)) wrgpioa_a2_in<-mkDWire(0);
265 // following wires capture signals to IO CELL if twi-0 is
267 Wire#(Bit#(1)) wrtwi_sda_out<-mkDWire(0);
268 Wire#(Bit#(1)) wrtwi_sda_outen<-mkDWire(0);
269 Wire#(Bit#(1)) wrtwi_sda_in<-mkDWire(0);
270 Wire#(Bit#(1)) wrtwi_scl_out<-mkDWire(0);
271 Wire#(Bit#(1)) wrtwi_scl_outen<-mkDWire(0);
272 Wire#(Bit#(1)) wrtwi_scl_in<-mkDWire(0);
275 /*====== This where the muxing starts for each io-cell======*/
276 Wire#(Bit#(1)) val0<-mkDWire(0); // need a zero
277 // output muxer for cell idx 0
279 wrcell0_mux==0?wrgpioa_a0_out:
280 wrcell0_mux==1?wruart_tx:
281 wrcell0_mux==2?val0: // unused
284 // outen muxer for cell idx 0
286 wrcell0_mux==0?wrgpioa_a0_outen: // bi-directional
287 wrcell0_mux==1?wrgpioa_a0_outen: // uart_tx is an output
288 wrcell0_mux==2?val0: // unused
289 wrtwi_sda_outen; // bi-directional
291 // priority-in-muxer for cell idx 0
292 rule assign_wrgpioa_a0_in_on_cell0(wrcell0_mux==0);
293 wrgpioa_a0_in<=cell0_mux_in;
296 rule assign_wrtwi_sda_in_on_cell0(wrcell0_mux==3);
297 wrtwi_sda_in<=cell0_mux_in;
300 // output muxer for cell idx 1
302 wrcell1_mux==0?wrgpioa_a1_out:
303 wrcell1_mux==1?val0: // uart_rx is an input
304 wrcell1_mux==2?wrtwi_sda_out:
307 // outen muxer for cell idx 1
309 wrcell1_mux==0?wrgpioa_a1_outen: // bi-directional
310 wrcell1_mux==1?val0: // uart_rx is an input
311 wrcell1_mux==2?wrtwi_sda_outen: // bi-directional
314 // priority-in-muxer for cell idx 1
315 rule assign_wrgpioa_a1_in_on_cell1(wrcell1_mux==0);
316 wrgpioa_a1_in<=cell1_mux_in;
319 rule assign_wruart_rx_on_cell1(wrcell1_mux==1);
320 wruart_rx<=cell1_mux_in;
323 rule assign_wrtwi_sda_in_on_cell1(wrcell1_mux==2);
324 wrtwi_sda_in<=cell1_mux_in;
327 // output muxer for cell idx 2
329 wrcell2_mux==0?wrgpioa_a2_out:
330 wrcell2_mux==1?val0: // unused
331 wrcell2_mux==2?wrtwi_scl_out:
334 // outen muxer for cell idx 2
336 wrcell2_mux==0?wrgpioa_a2_outen: // bi-directional
337 wrcell2_mux==1?val0: // unused
338 wrcell2_mux==2?wrtwi_scl_outen: // bi-directional
341 // priority-in-muxer for cell idx 2
342 rule assign_wrgpioa_a2_in_on_cell2(wrcell2_mux==0);
343 wrgpioa_a2_in<=cell2_mux_in;
346 rule assign_wrtwi_scl_in_on_cell2(wrcell2_mux==2);
347 wrtwi_scl_in<=cell2_mux_in;
351 /*=========================================*/
355 /*============================================================*/
357 interface mux_lines = interface MuxSelectionLines
359 method Action cell0_mux(Bit#(2) in);
363 method Action cell1_mux(Bit#(2) in);
367 method Action cell2_mux(Bit#(2) in);
373 interface iocell_side = interface IOCellSide
375 method io0_cell_out=cell0_mux_out;
376 method io0_cell_outen=cell0_mux_outen;
377 method Action io0_cell_in(Bit#(1) in);
381 method io1_cell_out=cell1_mux_out;
382 method io1_cell_outen=cell1_mux_outen;
383 method Action io1_cell_in(Bit#(1) in);
387 method io2_cell_out=cell2_mux_out;
388 method io2_cell_outen=cell2_mux_outen;
389 method Action io2_cell_in(Bit#(1) in);
394 interface peripheral_side= interface PeripheralSide
395 interface uart = interface PeripheralSideUART
396 // interface declaration between UART and pinmux
397 interface tx = interface Put
398 method Action put(Bit#(1) in);
402 interface rx = interface Get
403 method ActionValue#(Bit#(1)) get;
409 // interface peripheral_side = interface PeripheralSide
411 // interface uart = peripherals.uart;
412 // interface gpioa = peripherals.gpioa;
413 // interface twi = peripherals.twi;