src/test_bsv/tests/test_pinmux.py

   1 # Simple tests for an pinmux module
   2 import cocotb
   3 from cocotb.triggers import Timer
   4 from cocotb.result import TestFailure
   5 #from pinmux_model import pinmux_model
   6 import random
   7
   8
   9 """ dut is design under test """
  10
  11 """
  12 for gpio2, there are three ports at peripheral side:
  13     peripheral_side_gpioa_a2_out_in
  14     peripheral_side_gpioa_a2_outen_in
  15     peripheral_side_gpioa_a2_in
  16 """
  17 @cocotb.test()
  18 def pinmux_gpio2(dut):
  19     """Test for GPIO2"""
  20     yield Timer(2)
  21     # mux selection lines, each input two bit wide
  22     dut.mux_lines_cell2_mux_in = 0
  23     yield Timer(2)
  24     # enable input for mux
  25     dut.EN_mux_lines_cell0_mux = 0
  26     dut.EN_mux_lines_cell1_mux = 0
  27     dut.EN_mux_lines_cell2_mux = 1
  28
  29     yield Timer(2)
  30
  31     # GPIO2-out test
  32     # GPIO is inout peripheral
  33     dut.peripheral_side_gpioa_a2_out_in = 0
  34     dut.peripheral_side_gpioa_a2_outen_in = 1
  35
  36     yield Timer(2)
  37
  38     if dut.iocell_side_io2_cell_out != 0:  # output of iopad
  39         raise TestFailure(
  40             "gpioa_a2=0/mux=0/out=1 %s iocell_io2 != 0" %
  41             str(dut.iocell_side_io2_cell_out))
  42
  43     dut.peripheral_side_gpioa_a2_out_in = 1
  44
  45     yield Timer(2)
  46
  47     if dut.iocell_side_io2_cell_out != 1:
  48         raise TestFailure(
  49             "gpioa_a2=0/mux=0/out=1 %s iocell_io2 != 1" %
  50             str(dut.iocell_side_io2_cell_out))
  51
  52     # GPIO2-in test (first see if it's tri-state)
  53     #
  54     if str(dut.peripheral_side_gpioa_a2_in) != "x":
  55         raise TestFailure(
  56             "gpioa_a2=0/mux=0/out=1 %s gpio_a2_in != x" %
  57             str(dut.peripheral_side_gpioa_a2_in))
  58
  59     dut.peripheral_side_gpioa_a2_outen_in = 0
  60     dut.iocell_side_io2_cell_in_in = 0
  61     yield Timer(2)
  62
  63     if dut.peripheral_side_gpioa_a2_in != 0:
  64         raise TestFailure(
  65             "iocell_io2=0/mux=0/out=0 %s gpioa_a2 != 0" %
  66             str(dut.peripheral_side_gpioa_a2_in))
  67
  68     dut.iocell_side_io2_cell_in_in = 1
  69     yield Timer(2)
  70
  71     if dut.peripheral_side_gpioa_a2_in != 1:
  72         raise TestFailure(
  73             "iocell_io2=1/mux=0/out=0 %s gpioa_a2 != 1" %
  74             str(dut.peripheral_side_gpioa_a2_in))
  75
  76     dut.peripheral_side_gpioa_a2_outen_in = 1
  77     dut.iocell_side_io2_cell_in_in = 0
  78     yield Timer(2)
  79     dut._log.info("gpioa_a2_in %s" % dut.peripheral_side_gpioa_a2_in)
  80
  81     if dut.iocell_side_io2_cell_out != 1:
  82         raise TestFailure(
  83             "gpioa_a2=0/mux=0/out=1 %s iocell_io2 != 1" %
  84             str(dut.iocell_side_io2_cell_out))
  85
  86     dut._log.info("Ok!, gpio2 passed")
  87
  88 @cocotb.test()
  89 def pinmux_uart(dut):
  90     """Test for UART"""
  91     yield Timer(2)
  92     # mux selection lines, each input two bit wide
  93     dut.mux_lines_cell0_mux_in = 1
  94     yield Timer(2)
  95     # enable input for mux
  96     dut.EN_mux_lines_cell0_mux = 1
  97     dut.EN_mux_lines_cell1_mux = 0
  98     dut.EN_mux_lines_cell2_mux = 0
  99
 100     yield Timer(2)
 101
 102     # UART
 103     yield Timer(2)
 104     dut.peripheral_side_uart_tx_in = 1
 105     dut.peripheral_side_gpioa_a0_outen_in = 1
 106
 107     yield Timer(2)
 108
 109     if dut.iocell_side_io0_cell_out != 1:
 110         raise TestFailure(
 111             "uart_tx=1/mux=0/out=1 %s iocell_io0 != 1" %
 112             str(dut.iocell_side_io0_cell_out))
 113
 114     dut.peripheral_side_uart_tx_in = 0
 115
 116     yield Timer(2)
 117
 118     if dut.iocell_side_io0_cell_out != 0:
 119         raise TestFailure(
 120             "uart_tx=0/mux=0/out=1 %s iocell_io0 != 0" %
 121             str(dut.iocell_side_io0_cell_out))
 122
 123     dut._log.info("Ok!, uart passed")
 124
 125 @cocotb.test()
 126 def pinmux_twi_scl(dut):
 127     """Test for I2C SCL"""
 128     yield Timer(2)
 129     # mux selection lines, each input two bit wide
 130     dut.mux_lines_cell2_mux_in = 2
 131     yield Timer(2)
 132     # enable input for mux
 133     dut.EN_mux_lines_cell0_mux = 0
 134     dut.EN_mux_lines_cell1_mux = 0
 135     dut.EN_mux_lines_cell2_mux = 1
 136
 137     yield Timer(2)
 138
 139     # Test for out for twi_scl
 140     dut.peripheral_side_twi_scl_out_in = 0
 141     dut.peripheral_side_twi_scl_outen_in = 1
 142     yield Timer(2)
 143
 144     if dut.iocell_side_io2_cell_out != 0:
 145         raise TestFailure(
 146             "twi_scl=0/mux=0/out=1 %s iocell_io2 != 0" %
 147             str(dut.iocell_side_io2_cell_out))
 148
 149     dut.peripheral_side_twi_scl_out_in = 1
 150     yield Timer(2)
 151
 152     if dut.iocell_side_io2_cell_out != 1:
 153         raise TestFailure(
 154             "twi_scl=0/mux=0/out=1 %s iocell_io2 != 0" %
 155             str(dut.iocell_side_io2_cell_out))
 156
 157     dut._log.info("twi_scl_in %s" % dut.peripheral_side_twi_scl_in)
 158
 159     # Test for in
 160     dut.peripheral_side_twi_scl_outen_in = 0
 161     dut.iocell_side_io2_cell_in_in = 0
 162     yield Timer(2)
 163
 164     if dut.peripheral_side_twi_scl_in != 0:
 165         raise TestFailure(
 166             "iocell_io2=0/mux=0/out=0 %s twi_scl != 0" %
 167             str(dut.peripheral_side_twi_scl_in))
 168
 169     dut.iocell_side_io2_cell_in_in = 1
 170     yield Timer(2)
 171
 172     if dut.peripheral_side_twi_scl_in != 1:
 173         raise TestFailure(
 174             "iocell_io2=1/mux=0/out=0 %s twi_scl != 1" %
 175             str(dut.peripheral_side_twi_scl_in))
 176
 177     dut.peripheral_side_twi_scl_outen_in = 1
 178     dut.iocell_side_io2_cell_in_in = 0
 179     yield Timer(2)
 180     dut._log.info("twi_scl_in %s" % dut.peripheral_side_twi_scl_in)
 181
 182     if dut.iocell_side_io2_cell_out != 1:
 183         raise TestFailure(
 184             "twi_scl=0/mux=0/out=1 %s iocell_io2 != 1" %
 185             str(dut.iocell_side_io2_cell_out))
 186
 187     yield Timer(2)
 188
 189     dut._log.info("Ok!, twi_scl passed")
 190
 191 @cocotb.test()
 192 def pinmux_twi_sda(dut):
 193     """Test for I2C"""
 194     yield Timer(2)
 195     # mux selection lines, each input two bit wide
 196     dut.mux_lines_cell1_mux_in = 2
 197     yield Timer(2)
 198     # enable input for mux
 199     dut.EN_mux_lines_cell0_mux = 0
 200     dut.EN_mux_lines_cell1_mux = 1
 201     dut.EN_mux_lines_cell2_mux = 0
 202
 203     # TWI
 204     yield Timer(2)
 205     # define input variables
 206     dut.peripheral_side_twi_sda_out_in = 0
 207     dut.peripheral_side_twi_sda_outen_in = 1
 208
 209     yield Timer(2)
 210
 211     dut._log.info("io1_out %s" % dut.iocell_side_io1_cell_out)
 212     # Test for out for twi_sda
 213     if dut.iocell_side_io1_cell_out != 0:
 214         raise TestFailure(
 215             "twi_sda=0/mux=0/out=1 %s iocell_io1 != 0" %
 216             str(dut.iocell_side_io1_cell_out))
 217
 218     dut.peripheral_side_twi_sda_out_in = 1
 219     yield Timer(2)
 220
 221     if dut.iocell_side_io1_cell_out != 1:
 222         raise TestFailure(
 223             "twi_sda=1/mux=0/out=1 %s iocell_io1 != 1" %
 224             str(dut.iocell_side_io1_cell_out))
 225
 226     dut._log.info("twi_sda_in %s" % dut.peripheral_side_twi_sda_in)
 227
 228     # Test for in
 229     dut.peripheral_side_twi_sda_outen_in = 0
 230     dut.iocell_side_io1_cell_in_in = 0
 231     yield Timer(2)
 232
 233     if dut.peripheral_side_twi_sda_in != 0:
 234         raise TestFailure(
 235             "iocell_io1=0/mux=0/out=0 %s twi_sda != 0" %
 236             str(dut.peripheral_side_twi_sda_in))
 237
 238     dut.iocell_side_io1_cell_in_in = 1
 239     yield Timer(2)
 240
 241     if dut.peripheral_side_twi_sda_in != 1:
 242         raise TestFailure(
 243             "iocell_io1=1/mux=0/out=0 %s twi_sda != 1" %
 244             str(dut.peripheral_side_twi_sda_in))
 245
 246     dut.peripheral_side_twi_sda_outen_in = 1
 247     dut.iocell_side_io1_cell_in_in = 0
 248     yield Timer(2)
 249     dut._log.info("twi_sda_in %s" % dut.peripheral_side_twi_sda_in)
 250
 251     if dut.iocell_side_io1_cell_out != 1:
 252         raise TestFailure(
 253             "twi_sda=0/mux=0/out=1 %s iocell_io1 != 1" %
 254             str(dut.iocell_side_io1_cell_out))
 255
 256     yield Timer(2)
 257
 258     dut._log.info("Ok!, twi_sda passed")