test/vhdl/cocotb/controller/Makefile

   1 CURDIR=$(realpath .)
   2 TOPDIR=$(realpath ../../../..)
   3
   4 ifeq ($(PYTHONPATH),)
   5   PYTHONPATH := $(TOPDIR)
   6 else
   7   PYTHONPATH := $(TOPDIR):$(PYTHONPATH)
   8 endif
   9 export PYTHONPATH
  10
  11 VHDLDIR=$(TOPDIR)/c4m/vhdl/jtag
  12 VHDL_SOURCES = \
  13   $(VHDLDIR)/c4m_jtag_pkg.vhdl \
  14   $(VHDLDIR)/c4m_jtag_tap_fsm.vhdl \
  15   $(VHDLDIR)/c4m_jtag_irblock.vhdl \
  16   $(VHDLDIR)/c4m_jtag_iocell.vhdl \
  17   $(VHDLDIR)/c4m_jtag_ioblock.vhdl \
  18   $(VHDLDIR)/c4m_jtag_idblock.vhdl \
  19   $(VHDLDIR)/c4m_jtag_tap_controller.vhdl \
  20   $(CURDIR)/controller.vhdl
  21 #VHDL_SOURCES end
  22 TOPLEVEL=controller
  23 TOPLEVEL_LANG=vhdl
  24 MODULE=test
  25 SIM=ghdl
  26 GPI_IMPL=vhpi
  27 GHDL_ARGS=--std=08
  28 SIM_ARGS=--wave=test.ghw
  29
  30 COCOTBMAKEFILESDIR=$(shell cocotb-config --makefiles)
  31
  32 include $(COCOTBMAKEFILESDIR)/Makefile.inc
  33 include $(COCOTBMAKEFILESDIR)/Makefile.sim