fb67d263c47f58372fe6b8bab05e923abce64c6c
1 """ testing of InstructionQ
4 from copy
import deepcopy
5 from random
import randint
6 from nmigen
.compat
.sim
import run_simulation
7 from nmigen
.cli
import verilog
, rtlil
9 from soc
.scoreboard
.instruction_q
import InstructionQ
10 from nmutil
.nmoperator
import eq
15 def __init__(self
, dut
, iq
, n_in
, n_out
):
24 while i
< len(self
.iq
):
25 sendlen
= randint(1, self
.n_in
)
27 sendlen
= min(len(self
.iq
) - i
, sendlen
)
28 print("sendlen", len(self
.iq
)-i
, sendlen
)
29 for idx
in range(sendlen
):
30 instr
= self
.iq
[i
+idx
]
31 yield from eq(self
.dut
.data_i
[idx
], instr
)
32 di
= yield self
.dut
.data_i
[idx
] # .src1_i
33 print("senddata %d %x" % ((i
+idx
), di
))
35 yield self
.dut
.p_add_i
.eq(sendlen
)
37 o_p_ready
= yield self
.dut
.p_ready_o
40 o_p_ready
= yield self
.dut
.p_ready_o
42 yield self
.dut
.p_add_i
.eq(0)
44 print("send", len(self
.iq
), i
, sendlen
)
46 # wait random period of time before queueing another value
47 for j
in range(randint(0, 3)):
52 yield self
.dut
.p_add_i
.eq(0)
57 # wait random period of time before queueing another value
58 # for i in range(randint(0, 3)):
61 #send_range = randint(0, 3)
65 # send = randint(0, send_range) != 0
72 while i
< len(self
.iq
):
73 rcvlen
= randint(1, self
.n_out
)
74 #print ("outreq", rcvlen)
75 yield self
.dut
.n_sub_i
.eq(rcvlen
)
76 n_sub_o
= yield self
.dut
.n_sub_o
77 print("recv", n_sub_o
)
78 for j
in range(n_sub_o
):
79 r
= yield self
.dut
.data_o
[j
] # .src1_i
80 print("recvdata %x %s" % (r
, repr(self
.iq
[i
+j
])))
81 assert r
== self
.oq
[i
+j
]
85 yield self
.dut
.n_sub_i
.eq(0)
92 def mk_insns(n_insns
, wid
, opwid
):
94 for i
in range(n_insns
):
95 op1
= randint(0, (1 << wid
)-1)
97 op2
= randint(0, (1 << wid
)-1)
98 dst
= randint(0, (1 << wid
)-1)
99 oper
= randint(0, (1 << opwid
)-1)
100 imm
= randint(0, (1 << wid
)-1)
101 res
.append({'oper_i': oper
, 'opim_i': opi
,
102 'imm_i': imm
, 'dest_i': dst
,
103 'src1_i': op1
, 'src2_i': op2
})
107 @unittest.skip("test fails") # FIXME
114 dut
= InstructionQ(wid
, opwid
, qlen
, n_in
, n_out
)
115 insns
= mk_insns(1000, wid
, opwid
)
117 vl
= rtlil
.convert(dut
, ports
=dut
.ports())
118 with
open("test_iq.il", "w") as f
:
121 test
= IQSim(dut
, insns
, n_in
, n_out
)
123 run_simulation(dut
, [test
.rcv(), test
.send()
125 vcd_name
="test_iq.vcd")
128 if __name__
== '__main__':