1 // See LICENSE for license details.
5 `define DEBOUNCE_BITS 8
8 // Asynchronous reset input, should be held high until
9 // all clocks are locked and power is stable.
11 // Clock domains are brought up in increasing order
12 // All clocks are reset for at least 2^DEBOUNCE_BITS * period(clock1)
22 sifive_reset_hold hold_clock0(areset, clock1, reset1);
23 sifive_reset_sync sync_clock2(reset1, clock2, reset2);
24 sifive_reset_sync sync_clock3(reset2, clock3, reset3);
25 sifive_reset_sync sync_clock4(reset3, clock4, reset4);
28 // Assumes that areset is held for more than one clock
29 // Allows areset to be deasserted asynchronously
30 module sifive_reset_sync(
35 reg [`RESET_SYNC-1:0] gen_reset = {`RESET_SYNC{1'b1}};
36 always @(posedge clock, posedge areset) begin
38 gen_reset <= {`RESET_SYNC{1'b1}};
40 gen_reset <= {1'b0,gen_reset[`RESET_SYNC-1:1]};
43 assign reset = gen_reset[0];
46 module sifive_reset_hold(
52 reg [`RESET_SYNC-1:0] sync_reset = {`RESET_SYNC{1'b1}};
53 reg [`DEBOUNCE_BITS:0] debounce_reset = {`DEBOUNCE_BITS{1'b1}};
56 // Captures reset even if clock is not running
57 sifive_reset_sync capture(areset, clock, raw_reset);
59 // Remove any glitches due to runt areset
60 always @(posedge clock) begin
61 sync_reset <= {raw_reset,sync_reset[`RESET_SYNC-1:1]};
65 assign out_reset = debounce_reset[`DEBOUNCE_BITS];
66 always @(posedge clock) begin
67 if (sync_reset[0]) begin
68 debounce_reset <= {(`DEBOUNCE_BITS+1){1'b1}};
70 debounce_reset <= debounce_reset - out_reset;
74 assign reset = out_reset;