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Add test case for `riscv expose_custom`.
[riscv-tests.git]
/
debug
/
targets
/
RISC-V
/
spike32.py
diff --git
a/debug/targets/RISC-V/spike32.py
b/debug/targets/RISC-V/spike32.py
index 3bf8b4783c4578bb5f671b9036c5a08de37c7ab4..a831ecbb2af2ae63d9e5a0cbcfbe870885cefa0b 100644
(file)
--- a/
debug/targets/RISC-V/spike32.py
+++ b/
debug/targets/RISC-V/spike32.py
@@
-1,12
+1,20
@@
import targets
import testlib
import targets
import testlib
-class spike32
(targets.Targe
t):
+class spike32
_hart(targets.Har
t):
xlen = 32
ram = 0x10000000
ram_size = 0x10000000
instruction_hardware_breakpoint_count = 4
xlen = 32
ram = 0x10000000
ram_size = 0x10000000
instruction_hardware_breakpoint_count = 4
- reset_vector = 0x1000
+ reset_vectors = [0x1000]
+ link_script_path = "spike32.lds"
+
+class spike32(targets.Target):
+ harts = [spike32_hart()]
+ openocd_config_path = "spike-1.cfg"
+ timeout_sec = 30
+ implements_custom_test = True
def create(self):
def create(self):
- return testlib.Spike(self)
+ # 64-bit FPRs on 32-bit target
+ return testlib.Spike(self, isa="RV32IMAFDC")