+class Hart(object):
+ # XLEN of the hart. May be overridden with --32 or --64 command line
+ # options.
+ xlen = 0
+
+ # Will be autodetected (by running ExamineTarget) if left unset. Set to
+ # save a little time.
+ misa = None
+
+ # Path to linker script relative to the .py file where the target is
+ # defined. Defaults to <name>.lds.
+ link_script_path = None
+
+ # Implements dmode in tdata1 as described in the spec. Harts that need
+ # this value set to False are not compliant with the spec (but still usable
+ # as long as running code doesn't try to mess with triggers set by an
+ # external debugger).
+ honors_tdata1_hmode = True
+
+ # Address where a r/w/x block of RAM starts, together with its size.
+ ram = None
+ ram_size = None
+
+ # Number of instruction triggers the hart supports.
+ instruction_hardware_breakpoint_count = 0
+
+ # Defaults to target-<index>
+ name = None
+
+ # When reset, the PC must be at one of the values listed here.
+ # This is a list because on some boards the reset vector depends on
+ # jumpers.
+ reset_vectors = []
+
+ def extensionSupported(self, letter):
+ # target.misa is set by testlib.ExamineTarget
+ if self.misa:
+ return self.misa & (1 << (ord(letter.upper()) - ord('A')))
+ else:
+ return False
+