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Simplify fence.i test for RVC
[riscv-tests.git]
/
isa
/
rv64mi
/
dirty.S
diff --git
a/isa/rv64mi/dirty.S
b/isa/rv64mi/dirty.S
index f343cf913847fa01e5fd9d19d3b0ca69423135a9..0314cf5acbfc64914e89b388e90fc856f088ae0b 100644
(file)
--- a/
isa/rv64mi/dirty.S
+++ b/
isa/rv64mi/dirty.S
@@
-15,32
+15,36
@@
RVTEST_CODE_BEGIN
# Turn on VM with superpage identity mapping
la a1, page_table_1
# Turn on VM with superpage identity mapping
la a1, page_table_1
+ srl a1, a1, RISCV_PGSHIFT
+ la a2, page_table_2
+ srl a2, a2, RISCV_PGSHIFT
csrw sptbr, a1
sfence.vm
csrw sptbr, a1
sfence.vm
- li a1, ((MSTATUS_VM & ~(MSTATUS_VM<<1)) * VM_SV
43) | ((MSTATUS_PRV1 & ~(MSTATUS_PRV1
<<1)) * PRV_S)
+ li a1, ((MSTATUS_VM & ~(MSTATUS_VM<<1)) * VM_SV
39) | ((MSTATUS_MPP & ~(MSTATUS_MPP
<<1)) * PRV_S)
csrs mstatus, a1
csrs mstatus, a1
- la a1, 1f
+ la a1, 1f
- DRAM_BASE
csrw mepc, a1
csrw mepc, a1
- eret
+ la a1, stvec_handler - DRAM_BASE
+ csrw stvec, a1
+ mret
1:
# Try a faulting store to make sure dirty bit is not set
li TESTNUM, 2
li t0, 1
1:
# Try a faulting store to make sure dirty bit is not set
li TESTNUM, 2
li t0, 1
- s
d
t0, dummy, t1
+ s
w
t0, dummy, t1
# Load new page table
li TESTNUM, 3
# Load new page table
li TESTNUM, 3
- la t0, page_table_2
- csrw sptbr, t0
+ csrw sptbr, a2
sfence.vm
# Try a non-faulting store to make sure dirty bit is set
sfence.vm
# Try a non-faulting store to make sure dirty bit is set
- s
d
t0, dummy, t1
+ s
w
t0, dummy, t1
# Make sure R and D bits are set
lw t0, page_table_2
# Make sure R and D bits are set
lw t0, page_table_2
- li t1, PTE_
R
| PTE_D
+ li t1, PTE_
A
| PTE_D
and t0, t0, t1
bne t0, t1, die
and t0, t0, t1
bne t0, t1, die
@@
-48,13
+52,14
@@
RVTEST_CODE_BEGIN
TEST_PASSFAIL
TEST_PASSFAIL
+ .align 2
stvec_handler:
csrr t0, scause
li t1, 2
bne TESTNUM, t1, 1f
# Make sure R bit is set
lw t0, page_table_1
stvec_handler:
csrr t0, scause
li t1, 2
bne TESTNUM, t1, 1f
# Make sure R bit is set
lw t0, page_table_1
- li t1, PTE_
R
+ li t1, PTE_
A
and t0, t0, t1
bne t0, t1, die
and t0, t0, t1
bne t0, t1, die
@@
-72,11
+77,17
@@
stvec_handler:
die:
RVTEST_FAIL
die:
RVTEST_FAIL
-.data
-.align 13
-page_table_1: .dword PTE_V | PTE_SX | PTE_SR
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+.align 12
+page_table_1: .dword (DRAM_BASE/RISCV_PGSIZE << PTE_PPN_SHIFT) | PTE_V | PTE_U | PTE_R | PTE_X
dummy: .dword 0
dummy: .dword 0
-.align 1
3
-page_table_2: .dword
PTE_V | PTE_SX | PTE_SR | PTE_S
W
+.align 1
2
+page_table_2: .dword
(DRAM_BASE/RISCV_PGSIZE << PTE_PPN_SHIFT) | PTE_V | PTE_U | PTE_R | PTE_X | PTE_
W
-RVTEST_
CODE
_END
+RVTEST_
DATA
_END