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split out S-mode tests and M-mode tests
[riscv-tests.git]
/
isa
/
rv64si
/
scall.S
diff --git
a/isa/rv64si/scall.S
b/isa/rv64si/scall.S
index aa543e98c138471fd5ba869b098b2cced2e942b9..e1c13b6464ffcef7d3f718ea0d3b93222dc249dd 100644
(file)
--- a/
isa/rv64si/scall.S
+++ b/
isa/rv64si/scall.S
@@
-13,8
+13,13
@@
RVTEST_RV64S
RVTEST_CODE_BEGIN
RVTEST_RV64S
RVTEST_CODE_BEGIN
- la t0, stvec
- csrw stvec, t0
+#ifdef __MACHINE_MODE
+ #define sscratch mscratch
+ #define sstatus mstatus
+ #define scause mcause
+ #define sepc mepc
+ #define stvec_handler mtvec_handler
+#endif
li TESTNUM, 2
scall
li TESTNUM, 2
scall
@@
-24,7
+29,7
@@
RVTEST_CODE_BEGIN
TEST_PASSFAIL
TEST_PASSFAIL
-stvec:
+stvec
_handler
:
li t1, CAUSE_ECALL
csrr t0, scause
bne t0, t1, fail
li t1, CAUSE_ECALL
csrr t0, scause
bne t0, t1, fail