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Add another FP recoding test case
[riscv-tests.git]
/
isa
/
rv64sv
/
illegal_inst.S
diff --git
a/isa/rv64sv/illegal_inst.S
b/isa/rv64sv/illegal_inst.S
index add9918b71f6d6c5ba637f6297dc1dd18b22630a..7e653d1f077904271e76967ba4e67d79a3f2e99d 100644
(file)
--- a/
isa/rv64sv/illegal_inst.S
+++ b/
isa/rv64sv/illegal_inst.S
@@
-10,21
+10,9
@@
#include "riscv_test.h"
#include "test_macros.h"
#include "riscv_test.h"
#include "test_macros.h"
-RVTEST_RV64S
+RVTEST_RV64S
V
RVTEST_CODE_BEGIN
RVTEST_CODE_BEGIN
- li a0, SR_EA | SR_EI
- csrs status, a0
-
- la a3,handler
- csrw evec,a3 # set exception handler
-
- csrr a3,status
- li a4,(1 << IRQ_COP)
- slli a4,a4,SR_IM_SHIFT
- or a3,a3,a4 # enable IM[COP]
- csrw status,a3
-
.word 0xff00002b
vsetcfg 32,0
.word 0xff00002b
vsetcfg 32,0
@@
-39,18
+27,18
@@
vtcode2:
add x2,x2,x3
stop
add x2,x2,x3
stop
-handler:
+
stvec_
handler:
vxcptkill
li TESTNUM,2
# check cause
vxcptkill
li TESTNUM,2
# check cause
- vxcptcause a3
+ csrr a3, scause
li a4,HWACHA_CAUSE_ILLEGAL_INSTRUCTION
bne a3,a4,fail
# check vec irq aux
li a4,HWACHA_CAUSE_ILLEGAL_INSTRUCTION
bne a3,a4,fail
# check vec irq aux
- vxcptaux a3
+ csrr a3, sbadaddr
li a4, 0xff00002b
bne a3,a4,fail
li a4, 0xff00002b
bne a3,a4,fail