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Require little-endian host
[riscv-isa-sim.git]
/
riscv
/
decode.h
diff --git
a/riscv/decode.h
b/riscv/decode.h
index f4c7640bfd546b5540745b626c9e48d768a37e86..061b5b6249271152537fc2a4d299e17b5523c8a0 100644
(file)
--- a/
riscv/decode.h
+++ b/
riscv/decode.h
@@
-7,6
+7,10
@@
# error spike requires a two''s-complement c++ implementation
#endif
# error spike requires a two''s-complement c++ implementation
#endif
+#ifdef WORDS_BIGENDIAN
+# error spike requires a little-endian host
+#endif
+
#include <cstdint>
#include <string.h>
#include <strings.h>
#include <cstdint>
#include <string.h>
#include <strings.h>
@@
-202,9
+206,10
@@
private:
} while(0)
#define set_pc_and_serialize(x) \
} while(0)
#define set_pc_and_serialize(x) \
- do { set_pc(x); /* check alignment */ \
+ do { reg_t __npc = (x); \
+ set_pc(__npc); /* check alignment */ \
npc = PC_SERIALIZE_AFTER; \
npc = PC_SERIALIZE_AFTER; \
- STATE.pc =
(x)
; \
+ STATE.pc =
__npc
; \
} while(0)
/* Sentinel PC values to serialize simulator pipeline */
} while(0)
/* Sentinel PC values to serialize simulator pipeline */
@@
-234,8
+239,8
@@
private:
#define DEBUG_RAM_SIZE 64
#define DEBUG_RAM_END (DEBUG_RAM_START + DEBUG_RAM_SIZE)
#define DEBUG_END 0xfff
#define DEBUG_RAM_SIZE 64
#define DEBUG_RAM_END (DEBUG_RAM_START + DEBUG_RAM_SIZE)
#define DEBUG_END 0xfff
-#define DEBUG_CLEARDEBINT 0x10
8
-#define DEBUG_SETHALTNOT 0x10
0
+#define DEBUG_CLEARDEBINT 0x10
0
+#define DEBUG_SETHALTNOT 0x10
c
#define DEBUG_SIZE (DEBUG_END - DEBUG_START + 1)
#endif
#define DEBUG_SIZE (DEBUG_END - DEBUG_START + 1)
#endif