+ case CSR_CYCLE:
+ if ((state.mucounteren >> (which & (xlen-1))) & 1)
+ return get_csr(which + (CSR_MCYCLE - CSR_CYCLE));
+ break;
+ case CSR_STIME:
+ case CSR_SINSTRET:
+ case CSR_SCYCLE:
+ if ((state.mscounteren >> (which & (xlen-1))) & 1)
+ return get_csr(which + (CSR_MCYCLE - CSR_SCYCLE));
+ break;
+ case CSR_MUCOUNTEREN: return state.mucounteren;
+ case CSR_MSCOUNTEREN: return state.mscounteren;
+ case CSR_MUCYCLE_DELTA: return 0;
+ case CSR_MUTIME_DELTA: return 0;
+ case CSR_MUINSTRET_DELTA: return 0;
+ case CSR_MSCYCLE_DELTA: return 0;
+ case CSR_MSTIME_DELTA: return 0;
+ case CSR_MSINSTRET_DELTA: return 0;
+ case CSR_MUCYCLE_DELTAH: if (xlen > 32) break; else return 0;
+ case CSR_MUTIME_DELTAH: if (xlen > 32) break; else return 0;
+ case CSR_MUINSTRET_DELTAH: if (xlen > 32) break; else return 0;
+ case CSR_MSCYCLE_DELTAH: if (xlen > 32) break; else return 0;
+ case CSR_MSTIME_DELTAH: if (xlen > 32) break; else return 0;
+ case CSR_MSINSTRET_DELTAH: if (xlen > 32) break; else return 0;
+ case CSR_MCYCLE: return state.minstret;
+ case CSR_MINSTRET: return state.minstret;
+ case CSR_MCYCLEH: if (xlen > 32) break; else return state.minstret >> 32;
+ case CSR_MINSTRETH: if (xlen > 32) break; else return state.minstret >> 32;
+ case CSR_SSTATUS: {
+ reg_t mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP | SSTATUS_FS
+ | SSTATUS_XS | SSTATUS_PUM;
+ reg_t sstatus = state.mstatus & mask;
+ if ((sstatus & SSTATUS_FS) == SSTATUS_FS ||
+ (sstatus & SSTATUS_XS) == SSTATUS_XS)
+ sstatus |= (xlen == 32 ? SSTATUS32_SD : SSTATUS64_SD);
+ return sstatus;
+ }
+ case CSR_SIP: return state.mip & state.mideleg;
+ case CSR_SIE: return state.mie & state.mideleg;
+ case CSR_SEPC: return state.sepc;
+ case CSR_SBADADDR: return state.sbadaddr;
+ case CSR_STVEC: return state.stvec;
+ case CSR_SCAUSE:
+ if (max_xlen > xlen)
+ return state.scause | ((state.scause >> (max_xlen-1)) << (xlen-1));
+ return state.scause;
+ case CSR_SPTBR: return state.sptbr;
+ case CSR_SSCRATCH: return state.sscratch;
+ case CSR_MSTATUS: return state.mstatus;
+ case CSR_MIP: return state.mip;
+ case CSR_MIE: return state.mie;
+ case CSR_MEPC: return state.mepc;
+ case CSR_MSCRATCH: return state.mscratch;
+ case CSR_MCAUSE: return state.mcause;
+ case CSR_MBADADDR: return state.mbadaddr;
+ case CSR_MISA: return isa;
+ case CSR_MARCHID: return 0;
+ case CSR_MIMPID: return 0;
+ case CSR_MVENDORID: return 0;
+ case CSR_MHARTID: return id;
+ case CSR_MTVEC: return state.mtvec;
+ case CSR_MEDELEG: return state.medeleg;
+ case CSR_MIDELEG: return state.mideleg;
+ case CSR_TDRSELECT: return 0;
+ case CSR_DCSR:
+ {
+ uint32_t v = 0;
+ v = set_field(v, DCSR_XDEBUGVER, 1);
+ v = set_field(v, DCSR_HWBPCOUNT, 0);
+ v = set_field(v, DCSR_NDRESET, 0);
+ v = set_field(v, DCSR_FULLRESET, 0);
+ v = set_field(v, DCSR_PRV, state.dcsr.prv);
+ v = set_field(v, DCSR_STEP, state.dcsr.step);
+ v = set_field(v, DCSR_DEBUGINT, sim->debug_module.get_interrupt(id));
+ v = set_field(v, DCSR_STOPCYCLE, 0);
+ v = set_field(v, DCSR_STOPTIME, 0);
+ v = set_field(v, DCSR_EBREAKM, state.dcsr.ebreakm);
+ v = set_field(v, DCSR_EBREAKH, state.dcsr.ebreakh);
+ v = set_field(v, DCSR_EBREAKS, state.dcsr.ebreaks);
+ v = set_field(v, DCSR_EBREAKU, state.dcsr.ebreaku);
+ v = set_field(v, DCSR_HALT, state.dcsr.halt);
+ v = set_field(v, DCSR_CAUSE, state.dcsr.cause);
+ return v;
+ }
+ case CSR_DPC:
+ return state.dpc;
+ case CSR_DSCRATCH:
+ return state.dscratch;