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Don't force load trigger timing to After
[riscv-isa-sim.git]
/
riscv
/
processor.cc
diff --git
a/riscv/processor.cc
b/riscv/processor.cc
index 47a3a668fafe80a2bcebfaa4a60ecb1b59058781..f3764ae1e276265a30298dbd83a627d914b2bf13 100644
(file)
--- a/
riscv/processor.cc
+++ b/
riscv/processor.cc
@@
-437,8
+437,6
@@
void processor_t::set_csr(int which, reg_t val)
// Assume we're here because of csrw.
if (mc->execute)
mc->timing = 0;
// Assume we're here because of csrw.
if (mc->execute)
mc->timing = 0;
- if (mc->load)
- mc->timing = 1;
trigger_updated();
}
break;
trigger_updated();
}
break;