+ regfile_t<reg_t, NXPR, true> XPR;
+ regfile_t<freg_t, NFPR, false> FPR;
+
+ // control and status registers
+ reg_t prv;
+ reg_t mstatus;
+ reg_t mepc;
+ reg_t mbadaddr;
+ reg_t mscratch;
+ reg_t mtvec;
+ reg_t mcause;
+ reg_t minstret;
+ reg_t mie;
+ reg_t mip;
+ reg_t medeleg;
+ reg_t mideleg;
+ reg_t mucounteren;
+ reg_t mscounteren;
+ reg_t sepc;
+ reg_t sbadaddr;
+ reg_t sscratch;
+ reg_t stvec;
+ reg_t sptbr;
+ reg_t scause;
+ reg_t dpc;
+ reg_t dscratch;
+ dcsr_t dcsr;
+
+ uint32_t fflags;
+ uint32_t frm;
+ bool serialized; // whether timer CSRs are in a well-defined state
+
+ reg_t load_reservation;
+
+#ifdef RISCV_ENABLE_COMMITLOG
+ commit_log_reg_t log_reg_write;
+ reg_t last_inst_priv;
+#endif
+};
+
+typedef enum {
+ HR_NONE,
+ HR_STEPPED, // A single step was completed
+ HR_SWBP, // sbreak was executed
+ HR_INTERRUPT, // Execution interrupted by debugger
+ HR_CMDLINE, // Command line requested that the processor start halted
+ HR_ATTACHED // Halted because a debugger attached
+} halt_reason_t;
+
+// this class represents one processor in a RISC-V machine.
+class processor_t : public abstract_device_t
+{
+public:
+ processor_t(const char* isa, sim_t* sim, uint32_t id);
+ ~processor_t();
+
+ void set_debug(bool value);
+ void set_halted(bool value, halt_reason_t reason);
+ void set_single_step(bool value);
+ void set_histogram(bool value);
+ void reset(bool value);
+ void step(size_t n); // run for n cycles
+ bool running() { return run; }
+ void set_csr(int which, reg_t val);
+ void raise_interrupt(reg_t which);
+ reg_t get_csr(int which);
+ mmu_t* get_mmu() { return mmu; }
+ state_t* get_state() { return &state; }
+ extension_t* get_extension() { return ext; }
+ bool supports_extension(unsigned char ext) {
+ if (ext >= 'a' && ext <= 'z') ext += 'A' - 'a';
+ return ext >= 'A' && ext <= 'Z' && ((isa >> (ext - 'A')) & 1);
+ }
+ void set_privilege(reg_t);
+ void yield_load_reservation() { state.load_reservation = (reg_t)-1; }
+ void update_histogram(reg_t pc);