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Merge pull request #113 from riscv/debug_readme
[riscv-isa-sim.git]
/
riscv
/
riscv.mk.in
diff --git
a/riscv/riscv.mk.in
b/riscv/riscv.mk.in
index 18d91c569433d2543f34724c4f342f6f0c3cd535..05e316a438ad4dd68e1e9f2646328afc1d5c1758 100644
(file)
--- a/
riscv/riscv.mk.in
+++ b/
riscv/riscv.mk.in
@@
-7,7
+7,6
@@
riscv_subproject_deps = \
riscv_install_prog_srcs = \
riscv_hdrs = \
riscv_install_prog_srcs = \
riscv_hdrs = \
- htif.h \
common.h \
decode.h \
devices.h \
common.h \
decode.h \
devices.h \
@@
-24,12
+23,14
@@
riscv_hdrs = \
rocc.h \
insn_template.h \
mulhi.h \
rocc.h \
insn_template.h \
mulhi.h \
+ debug_module.h \
+ remote_bitbang.h \
+ jtag_dtm.h \
riscv_precompiled_hdrs = \
insn_template.h \
riscv_srcs = \
riscv_precompiled_hdrs = \
insn_template.h \
riscv_srcs = \
- htif.cc \
processor.cc \
execute.cc \
sim.cc \
processor.cc \
execute.cc \
sim.cc \
@@
-44,7
+45,10
@@
riscv_srcs = \
regnames.cc \
devices.cc \
rom.cc \
regnames.cc \
devices.cc \
rom.cc \
- rtc.cc \
+ clint.cc \
+ debug_module.cc \
+ remote_bitbang.cc \
+ jtag_dtm.cc \
$(riscv_gen_srcs) \
riscv_test_srcs =
$(riscv_gen_srcs) \
riscv_test_srcs =
@@
-130,6
+134,7
@@
riscv_insn_list = \
divu \
divuw \
divw \
divu \
divuw \
divw \
+ dret \
ebreak \
ecall \
fadd_d \
ebreak \
ecall \
fadd_d \
@@
-177,9
+182,9
@@
riscv_insn_list = \
fmul_d \
fmul_s \
fmv_d_x \
fmul_d \
fmul_s \
fmv_d_x \
- fmv_
s
_x \
+ fmv_
w
_x \
fmv_x_d \
fmv_x_d \
- fmv_x_
s
\
+ fmv_x_
w
\
fnmadd_d \
fnmadd_s \
fnmsub_d \
fnmadd_d \
fnmadd_s \
fnmsub_d \
@@
-224,7
+229,7
@@
riscv_insn_list = \
sc_d \
sc_w \
sd \
sc_d \
sc_w \
sd \
- sfence_vm \
+ sfence_vm
a
\
sh \
sll \
slli \
sh \
sll \
slli \