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debug: Compiles again with new debug_defines.h file, but not tested.
[riscv-isa-sim.git]
/
riscv
/
riscv.mk.in
diff --git
a/riscv/riscv.mk.in
b/riscv/riscv.mk.in
index 65f8c99a84936ccc0cc053be38884eaf6552cbb9..40054cfbaa289793f4ca8051dc1edf0157be20e4 100644
(file)
--- a/
riscv/riscv.mk.in
+++ b/
riscv/riscv.mk.in
@@
-7,7
+7,6
@@
riscv_subproject_deps = \
riscv_install_prog_srcs = \
riscv_hdrs = \
riscv_install_prog_srcs = \
riscv_hdrs = \
- htif.h \
common.h \
decode.h \
devices.h \
common.h \
decode.h \
devices.h \
@@
-24,14
+23,14
@@
riscv_hdrs = \
rocc.h \
insn_template.h \
mulhi.h \
rocc.h \
insn_template.h \
mulhi.h \
- gdbserver.h \
debug_module.h \
debug_module.h \
+ remote_bitbang.h \
+ jtag_dtm.h \
riscv_precompiled_hdrs = \
insn_template.h \
riscv_srcs = \
riscv_precompiled_hdrs = \
insn_template.h \
riscv_srcs = \
- htif.cc \
processor.cc \
execute.cc \
sim.cc \
processor.cc \
execute.cc \
sim.cc \
@@
-46,9
+45,10
@@
riscv_srcs = \
regnames.cc \
devices.cc \
rom.cc \
regnames.cc \
devices.cc \
rom.cc \
- rtc.cc \
- gdbserver.cc \
+ clint.cc \
debug_module.cc \
debug_module.cc \
+ remote_bitbang.cc \
+ jtag_dtm.cc \
$(riscv_gen_srcs) \
riscv_test_srcs =
$(riscv_gen_srcs) \
riscv_test_srcs =
@@
-229,7
+229,7
@@
riscv_insn_list = \
sc_d \
sc_w \
sd \
sc_d \
sc_w \
sd \
- sfence_vm \
+ sfence_vm
a
\
sh \
sll \
slli \
sh \
sll \
slli \