- if(args.size() != 1)
- throw trap_illegal_instruction;
-
- reg_t addr = strtol(args[0].c_str(),NULL,16), val;
- if(addr == LONG_MAX)
- addr = strtoul(args[0].c_str(),NULL,16);
-
- mmu_t mmu(mem,memsz);
- switch(addr % 8)
- {
- case 0:
- val = mmu.load_uint64(addr);
- break;
- case 4:
- val = mmu.load_uint32(addr);
- break;
- case 2:
- case 6:
- val = mmu.load_uint16(addr);
- break;
- default:
- val = mmu.load_uint8(addr);
- break;
+ reg_t rtc_addr = EXT_IO_BASE;
+ bus.add_device(rtc_addr, rtc.get());
+
+ const int align = 0x1000;
+ reg_t cpu_addr = rtc_addr + ((rtc->size() - 1) / align + 1) * align;
+ reg_t cpu_size = align;
+
+ uint32_t reset_vec[8] = {
+ 0x297 + DRAM_BASE - DEFAULT_RSTVEC, // reset vector
+ 0x00028067, // jump straight to DRAM_BASE
+ 0x00000000, // reserved
+ 0, // config string pointer
+ 0, 0, 0, 0 // trap vector
+ };
+ reset_vec[3] = DEFAULT_RSTVEC + sizeof(reset_vec); // config string pointer
+
+ std::vector<char> rom((char*)reset_vec, (char*)reset_vec + sizeof(reset_vec));
+
+ std::stringstream s;
+ s << std::dec <<
+ "/dts-v1/;\n"
+ "\n"
+ "/ {\n"
+ " #address-cells = <2>;\n"
+ " #size-cells = <2>;\n"
+ " compatible = \"ucbbar,spike-bare-dev\";\n"
+ " model = \"ucbbar,spike-bare\";\n"
+ " cpus {\n"
+ " #address-cells = <1>;\n"
+ " #size-cells = <0>;\n"
+ " timebase-frequency = <" << (CPU_HZ/INSNS_PER_RTC_TICK) << ">;\n";
+ for (size_t i = 0; i < procs.size(); i++) {
+ s << " CPU" << i << ": cpu@" << i << " {\n"
+ " device_type = \"cpu\";\n"
+ " reg = <" << i << ">;\n"
+ " status = \"okay\";\n"
+ " compatible = \"riscv\";\n"
+ " riscv,isa = \"" << procs[i]->isa_string << "\";\n"
+ " mmu-type = \"riscv," << (procs[i]->max_xlen <= 32 ? "sv32" : "sv48") << "\";\n"
+ " clock-frequency = <" << CPU_HZ << ">;\n"
+ " };\n";