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Merge pull request #35 from sifive/spi-buffers
[sifive-blocks.git]
/
src
/
main
/
scala
/
devices
/
spi
/
SPIPeriphery.scala
diff --git
a/src/main/scala/devices/spi/SPIPeriphery.scala
b/src/main/scala/devices/spi/SPIPeriphery.scala
index 80978946103eec972449e71d82227beceb2b3e86..595ffc3527e18b08ccd884b7d15ec349771fb4e5 100644
(file)
--- a/
src/main/scala/devices/spi/SPIPeriphery.scala
+++ b/
src/main/scala/devices/spi/SPIPeriphery.scala
@@
-4,8
+4,8
@@
package sifive.blocks.devices.spi
import Chisel._
import freechips.rocketchip.config.Field
import freechips.rocketchip.coreplex.{HasPeripheryBus, HasInterruptBus}
import Chisel._
import freechips.rocketchip.config.Field
import freechips.rocketchip.coreplex.{HasPeripheryBus, HasInterruptBus}
-import freechips.rocketchip.diplomacy.{LazyModule,LazyMultiIOModuleImp}
-import freechips.rocketchip.tilelink.{TLFragmenter}
+import freechips.rocketchip.diplomacy.{LazyModule,LazyMultiIOModuleImp
,BufferParams
}
+import freechips.rocketchip.tilelink.{TLFragmenter
,TLBuffer
}
import freechips.rocketchip.util.HeterogeneousBag
case object PeripherySPIKey extends Field[Seq[SPIParams]]
import freechips.rocketchip.util.HeterogeneousBag
case object PeripherySPIKey extends Field[Seq[SPIParams]]
@@
-41,7
+41,10
@@
trait HasPeripherySPIFlash extends HasPeripheryBus with HasInterruptBus {
val qspis = spiFlashParams map { params =>
val qspi = LazyModule(new TLSPIFlash(pbus.beatBytes, params))
qspi.rnode := pbus.toVariableWidthSlaves
val qspis = spiFlashParams map { params =>
val qspi = LazyModule(new TLSPIFlash(pbus.beatBytes, params))
qspi.rnode := pbus.toVariableWidthSlaves
- qspi.fnode := TLFragmenter(1, pbus.blockBytes)(pbus.toFixedWidthSlaves)
+ qspi.fnode :=
+ TLFragmenter(1, pbus.blockBytes)(
+ TLBuffer(BufferParams(params.fBufferDepth), BufferParams.none)(
+ pbus.toFixedWidthSlaves))
ibus.fromSync := qspi.intnode
qspi
}
ibus.fromSync := qspi.intnode
qspi
}