val xilinxvc707mig = LazyModule(new XilinxVC707MIG)
require(p(BankedL2Config).nMemoryChannels == 1, "Coreplex must have 1 master memory port")
xilinxvc707mig.node := mem(0).node
}
val xilinxvc707mig = LazyModule(new XilinxVC707MIG)
require(p(BankedL2Config).nMemoryChannels == 1, "Coreplex must have 1 master memory port")
xilinxvc707mig.node := mem(0).node
}