-trait HasPeripheryXilinxVC707PCIeX1Bundle extends HasTopLevelNetworksBundle {
- val xilinxvc707pcie = new XilinxVC707PCIeX1IO
+trait HasPeripheryXilinxVC707PCIeX1Bundle {
+ val xilinxvc707pcie: XilinxVC707PCIeX1IO
+ def connectXilinxVC707PCIeX1ToPads(pads: XilinxVC707PCIeX1Pads) {
+ pads <> xilinxvc707pcie
+ }