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vc707mig: use an external ibuf
[sifive-blocks.git]
/
src
/
main
/
scala
/
ip
/
xilinx
/
vc707mig
/
vc707mig.scala
diff --git
a/src/main/scala/ip/xilinx/vc707mig/vc707mig.scala
b/src/main/scala/ip/xilinx/vc707mig/vc707mig.scala
index 6f281ecbaea0ce9d9015a8ac7a42f9913fc37dd3..d7b522fd7eaa0ab38c7a67638387353fe60ddeb5 100644
(file)
--- a/
src/main/scala/ip/xilinx/vc707mig/vc707mig.scala
+++ b/
src/main/scala/ip/xilinx/vc707mig/vc707mig.scala
@@
-31,9
+31,8
@@
trait VC707MIGIODDR extends Bundle {
//reused directly in io bundle for sifive.blocks.devices.xilinxvc707mig
trait VC707MIGIOClocksReset extends Bundle {
//inputs
//reused directly in io bundle for sifive.blocks.devices.xilinxvc707mig
trait VC707MIGIOClocksReset extends Bundle {
//inputs
- //differential system clocks
- val sys_clk_n = Bool(INPUT)
- val sys_clk_p = Bool(INPUT)
+ //"NO_BUFFER" clock source (must be connected to IBUF outside of IP)
+ val sys_clk_i = Bool(INPUT)
//user interface signals
val ui_clk = Clock(OUTPUT)
val ui_clk_sync_rst = Bool(OUTPUT)
//user interface signals
val ui_clk = Clock(OUTPUT)
val ui_clk_sync_rst = Bool(OUTPUT)