The main message here: **use the right tool for the right job**.
* mailing list: general communication and discussion.
+* irc channel #libre-soc: real(ish)-time communication.
* bugtracker: task-orientated, goal-orientated *focussed* discussion.
* ikiwiki: document store, information store, and (editable) main website
* git repositories: code stores (**not binary or auto-generated output store**)
-* ftp server (<https://ftp.libre-soc.org/>): large file store.
+* ftp server (<https://ftp.libre-soc.org/>): large (temporary,
+ auto-generated) file store.
we will add an IRC channel at some point when there are enough people
to warrant having one (and it will be publicly archived)
public and archived (i.e not skype, not telegram, not discord,
and anyone seriously suggesting slack will be thrown to the
lions). Therefore we have a mailing list. Everything goes through
-there. <https://lists.libre-soc.org/mailman/listinfo/libre-riscv-dev>
+there. <https://lists.libre-soc.org/mailman/listinfo/libre-soc-dev>
therefore please do google "mailing list etiquette" and at the very
minimum look up and understand the following:
If discussions result in any actionable items, it is important not to
lose track of them. Create a bugreport, find the discussion in the
-archives <https://lists.libre-soc.org/pipermail/libre-riscv-dev/>,
+archives <https://lists.libre-soc.org/pipermail/libre-soc-dev/>,
and put the link actually in the bugtracker as one of the comments.
At some point in any discussion, the sudden realisation may dawn on one
../configure --srcdir=.. --host=x86_64-linux --target=powerpc64-linux-gnu
make -j$(nproc)
make install
-
+
## power_instruction_analyzer (pia)
We have a custom tool built in rust by programmerjake to help analyze
the power instructions execution on *actual* hardware.
+Note: a very recent version of pip3 is required for this to work.
+
Install rust:
curl --proto '=https' --tlsv1.2 -sSf https://sh.rustup.rs | sh
git clone https://salsa.debian.org/Kazan-team/power-instruction-analyzer.git pia
cd pia
maturin build --cargo-extra-args=--features=python-extension
+ python3 -m pip install --user target/wheels/*.whl
+
+Note: an ongoing bug in maturin interferes with successful installation. This can be worked around by explicitly installing only the .whl files needed rather than installing everything (*.whl).
+
+## Chips4Makers JTAG
+
+As this is an actual ASIC, we do not rely on an FPGA's JTAG TAP interface, instead require a full complete independent implementation of JTAG. Staf Verhaegen has one, with a full test suite, and it is superb and well-written. The Libre-SOC version includes DMI (Debug Memory Interface):
+
+ git clone https://git.libre-soc.org/git/c4m-jtag.git/
-Get a root prompt by doing sudo bash then:
+Included is an IDCODE tap point, Wishbone Master (for direct memory read and write, fully independent of the core), IOPad redirection and testing, and general purpose shift register capability for any custom use.
- cd /home/USERNAME/src/pia
- python3 -m pip install target/wheels/*.whl
+We added a DMI to JTAG bridge in LibreSOC which is directly connected to the core, to access registers and to be able to start and stop the core and change the PC. In combination with the JTAG Wishbone interface the test ASIC can have a bootloader uploaded directly into onboard SRAM and execution begun.
## Coriolis2
-See [[coriolis2]] page, for those people doing layout work.
+See [[HDL_workflow/coriolis2]] page, for those people doing layout work.
# Registering for git repository access
* cd !$
* git clone gitolite3@git.libre-soc.org:nmutil.git
* git clone gitolite3@git.libre-soc.org:ieee754fpu.git
+* git clone gitolite3@git.libre-soc.org:nmigen-soc.git
* git clone gitolite3@git.libre-soc.org:soc.git
In each of these directories, in the order listed, track down the
projects / libreriscv.git / blobdiff